Invention Grant
- Patent Title: Method for manufacturing a FinFET device with a backside power rail and a backside self-aligned via by etching an extended source trench
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Application No.: US17081894Application Date: 2020-10-27
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Publication No.: US11362213B2Publication Date: 2022-06-14
- Inventor: Shi Ning Ju , Kuo-Cheng Chiang , Chih-Hao Wang , Kuan-Lun Cheng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L23/522 ; H01L23/528 ; H01L21/8234 ; H01L29/66 ; H01L21/768 ; H01L29/417 ; H01L21/762 ; H01L27/092 ; H01L27/088

Abstract:
A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.
Public/Granted literature
- US20210305428A1 FINFET DEVICES WITH BACKSIDE POWER RAIL AND BACKSIDE SELF-ALIGNED VIA Public/Granted day:2021-09-30
Information query
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