Invention Grant
- Patent Title: Forming openings at intersection of cutting lines
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Application No.: US16605878Application Date: 2018-02-09
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Publication No.: US11367655B2Publication Date: 2022-06-21
- Inventor: Tomoya Taguchi , Takeshi Sakamoto
- Applicant: HAMAMATSU PHOTONICS K.K.
- Applicant Address: JP Hamamatsu
- Assignee: HAMAMATSU PHOTONICS K.K.
- Current Assignee: HAMAMATSU PHOTONICS K.K.
- Current Assignee Address: JP Hamamatsu
- Agency: Faegre Drinker Biddle & Reath LLP
- Priority: JPJP2017-082256 20170418
- International Application: PCT/JP2018/004716 WO 20180209
- International Announcement: WO2018/193693 WO 20181025
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L21/268 ; H01L21/3065 ; H01L21/308 ; H01L23/00 ; B23K26/53 ; H01L21/304

Abstract:
A chip production method includes a first step of setting a first cutting line and a second cutting line on a substrate including a plurality of functional elements, a second step of forming a mask on the substrate such that the functional elements are covered and an intersection region including an intersection of the first cutting line and the second cutting line is exposed, a third step of removing the intersection region from the substrate and forming a penetration hole by etching the substrate using the mask, a fourth step of forming a modified region in the substrate along the first cutting line, a fifth step of forming a modified region in the substrate along the second cutting line, and a sixth step of forming chips by cutting the substrate along the first cutting line and the second cutting line.
Public/Granted literature
- US20210125868A1 CHIP PRODUCTION METHOD, AND, SILICON CHIP Public/Granted day:2021-04-29
Information query
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