- 专利标题: Interconnect structure for fin-like field effect transistor
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申请号: US17120563申请日: 2020-12-14
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公开(公告)号: US11367663B2公开(公告)日: 2022-06-21
- 发明人: Jhon Jhy Liaw
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Haynes and Boone, LLP
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238 ; H01L21/768 ; H01L23/522 ; H01L23/528 ; H01L27/092 ; H01L29/08
摘要:
Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.
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