In an embodiment, a local memory that is dedicated to one or more hardware accelerators is divided into a plurality of independently powerable sections. That is, one or more of the sections may be powered on while other ones of the plurality of sections are powered off. The hardware accelerators receive instruction words from one or more central processing units (CPUs). The instruction words may include a field that specifies an amount of the memory that is used when processing the first instruction word, and the power control circuit may be configured to power a subset of the plurality of sections to provide sufficient memory for the instruction word based on the field, while one or more of the plurality of sections are powered off.