Invention Grant
- Patent Title: Transistors with high concentration of germanium
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Application No.: US16707490Application Date: 2019-12-09
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Publication No.: US11387320B2Publication Date: 2022-07-12
- Inventor: Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Kinney & Lange, P. A.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/285 ; H01L29/165 ; H01L29/45 ; H01L29/49 ; H01L29/66 ; H01L29/78 ; H01L29/423 ; H01L21/768 ; H01L29/167 ; H01L21/02 ; H01L29/08 ; H01L29/36 ; H01L27/092 ; H01L23/535 ; H01L29/417 ; H01L21/3215 ; H01L29/778

Abstract:
Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
Information query
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