公开(公告)号：US12027417B2

公开(公告)日：2024-07-02

申请号：US16913320

申请日：2020-06-26

申请人： Intel Corporation

发明人： Cory Bomberger ,  Suresh Vishwanath ,  Yulia Tolstova ,  Pratik Patel ,  Szuya S. Liao ,  Anand S. Murthy

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L21/76834 ,  H01L21/02532 ,  H01L21/28255 ,  H01L21/3215 ,  H01L21/76831 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66628

摘要： Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.

公开(公告)号：US20240105510A1

公开(公告)日：2024-03-28

申请号：US17950640

申请日：2022-09-22

申请人： Micron Technology, Inc.

发明人： Yiping Wang ,  Wesley O. Mckinsey

IPC分类号： H01L21/768 ,  H01L21/3215 ,  H01L23/532 ,  H01L23/535

CPC分类号： H01L21/76886 ,  H01L21/32155 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/53271 ,  H01L23/535

摘要： Methods, systems, and devices for plasma-doped trenches for memory are described. A method for forming a memory device with plasma-doped trenches may include forming a stack of materials having alternating layers of polysilicon and oxide materials. A trench may be etched in the stack and doped using a plasma doping process. In some examples, the trench may be doped by applying Boron fluoride, diborane, methane, or Boron and Carbon Hydride gases diluted with Hydrogen (H2) or Helium to the sidewalls and bottom surface of the trench, which may dope portions of the polysilicon material with Boron, Carbon, Fluorine, Helium, or Hydrogen.

公开(公告)号：US11830877B2

公开(公告)日：2023-11-28

申请号：US16688222

申请日：2019-11-19

申请人： International Business Machines Corporation

发明人： Takashi Ando ,  Jingyun Zhang ,  Choonghyun Lee ,  Pouya Hashemi ,  Alexander Reznicek

IPC分类号： H01L21/8238 ,  H01L21/3215 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L27/0922 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/3215 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78651 ,  H01L29/78696

摘要： Embodiments of the invention are directed to a configuration of nanosheet FET devices in a first region of a substrate. Each of the nanosheet FET devices in the first region includes a first channel nanosheet, a second channel nanosheet over the first channel nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein the first gate structure and the second gate structure pinch off in a pinch off area between the first gate structure and the second gate structure. The first gate structure includes a doped region, and the second gate structure includes a doped region. At least a portion of the pinch off area is undoped.

公开(公告)号：US20230377873A1

公开(公告)日：2023-11-23

申请号：US18361743

申请日：2023-07-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Chang Wen ,  Chang-Yun Chang ,  Hsien-Chin Lin ,  Hung-Kai Chen

IPC分类号： H01L21/02 ,  H01L21/3215 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/8238

CPC分类号： H01L21/0214 ,  H01L21/32155 ,  H01L21/31056 ,  H01L21/02164 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7848 ,  H01L21/8258 ,  H01L21/823814 ,  H01L29/785 ,  H01L21/76224

摘要： A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.

公开(公告)号：US11721544B2

公开(公告)日：2023-08-08

申请号：US17588883

申请日：2022-01-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Chang Wen ,  Chang-Yun Chang ,  Hsien-Chin Lin ,  Hung-Kai Chen

IPC分类号： H01L21/02 ,  H01L21/3215 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/8238 ,  H01L21/762 ,  H01L27/02 ,  H10B10/00

CPC分类号： H01L21/0214 ,  H01L21/02164 ,  H01L21/31056 ,  H01L21/32155 ,  H01L21/8258 ,  H01L21/823814 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7848 ,  H01L21/76224 ,  H01L27/0207 ,  H10B10/12

摘要： A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.

公开(公告)号：US11715739B2

公开(公告)日：2023-08-01

申请号：US17338738

申请日：2021-06-04

申请人： Samsung Display Co., Ltd.

发明人： Jong Oh Seo ,  Jong Jun Baek

IPC分类号： H01L27/32 ,  H01L51/56 ,  H01L27/12 ,  H01L29/786 ,  H01L21/3215 ,  H01L21/02 ,  H10K59/124 ,  H10K71/00 ,  H10K59/123 ,  H10K59/12

CPC分类号： H01L27/1222 ,  H01L21/02068 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02675 ,  H01L21/32155 ,  H01L27/1274 ,  H01L29/78696 ,  H10K59/124 ,  H10K71/00 ,  H10K59/1201 ,  H10K59/123

摘要： An embodiment provides a manufacturing method of a polycrystalline silicon layer, including: forming a first amorphous silicon layer on a substrate; doping an N-type impurity into the first amorphous silicon layer; forming a second amorphous silicon layer on the n-doped first amorphous silicon layer; doping a P-type impurity into the second amorphous silicon layer; and crystalizing the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer by irradiating a laser beam onto n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer to form a polycrystalline silicon layer.

公开(公告)号：US11710696B2

公开(公告)日：2023-07-25

申请号：US17678232

申请日：2022-02-23

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang Chiu ,  Tse-Yao Huang

IPC分类号： H01L23/00 ,  H01L23/525 ,  H01L23/535 ,  H01L21/3215 ,  H01L29/92 ,  H01L21/28 ,  H01L29/40 ,  H01L23/532 ,  H01L29/49

CPC分类号： H01L23/5252 ,  H01L21/28158 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/401 ,  H01L29/92 ,  H01L23/53271 ,  H01L29/495

摘要： The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device including a substrate, a bottom conductive layer positioned in the substrate, a first gate structure including a first gate dielectric layer positioned on the bottom conductive layer, a first work function layer positioned on the first gate dielectric layer, and a first filler layer positioned on the first work function layer, a second gate structure including a second gate dielectric layer positioned on the bottom conductive layer and spaced apart from the first gate dielectric layer, a second work function layer positioned on the second gate dielectric layer, and a second filler layer positioned on the second work function layer, a conductive plug electrically coupled to the bottom conductive layer, and a top conductive layer electrically coupled to the first gate structure and the second gate structure.

公开(公告)号：US20230209822A1

公开(公告)日：2023-06-29

申请号：US18117989

申请日：2023-03-06

申请人： Micron Technology, Inc.

发明人： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC分类号： H10B41/35 ,  H01L21/308 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/67 ,  H01L21/3215 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27

CPC分类号： H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3215 ,  H01L21/31144 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

摘要： Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11651925B2

公开(公告)日：2023-05-16

申请号：US17146515

申请日：2021-01-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Joshua T. Smith ,  Benjamin Wunsch

IPC分类号： H01L21/00 ,  H01J21/10 ,  H01J1/304 ,  H01L21/3215 ,  H01L29/417

CPC分类号： H01J21/105 ,  H01J1/3042 ,  H01L21/3215 ,  H01L29/41725 ,  H01J2201/319

摘要： A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

公开(公告)号：US20230122969A1

公开(公告)日：2023-04-20

申请号：US18067415

申请日：2022-12-16

申请人： Applied Materials, Inc.

发明人： Shirish PETHE ,  Fuhong ZHANG ,  Joung Joo LEE ,  Rui LI ,  Xiangjin XIE ,  Xianmin TANG

IPC分类号： H01L21/768 ,  H01L21/3215 ,  H01L21/3213

摘要： Embodiments disclosed herein generally relate to methods of depositing a plurality of layers. A doped copper seed layer is deposited in a plurality of feature definitions in a device structure. A first copper seed layer is deposited and then the first copper seed layer is doped to form a doped copper seed layer, or a doped copper seed layer is deposited directly. The doped copper seed layer leads to increased flowability, reducing poor step coverage, overhang, and voids in the copper layer.