- 专利标题: Inter-poly connection for parasitic capacitor and die size improvement
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申请号: US16122180申请日: 2018-09-05
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公开(公告)号: US11407636B2公开(公告)日: 2022-08-09
- 发明人: Shyh-Wei Cheng , Chih-Yu Wang , Hsi-Cheng Hsu , Ji-Hong Chiang , Jui-Chun Weng , Shiuan-Jeng Lin , Wei-Ding Wu , Ching-Hsiang Hu
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Eschweiler & Potashnik, LLC
- 主分类号: B81B7/00
- IPC分类号: B81B7/00 ; B81C1/00
摘要:
The present disclosure, in some embodiments, relates to a method of forming a micro-electromechanical system (MEMS) package. The method includes forming one or more depressions within a capping substrate. A back-side of a MEMS substrate is bonded to the capping substrate after forming the one or more depressions, so that the one or more depressions define one or more cavities between the capping substrate and the MEMS substrate. A front-side of the MEMS substrate is selectively etched to form one or more trenches extending through the MEMS substrate, and one or more polysilicon vias are formed within the one or more trenches. A conductive bonding structure is formed on the front-side of the MEMS substrate at a location contacting the one or more polysilicon vias. The MEMS substrate is bonded to a CMOS substrate having one or more semiconductor devices by way of the conductive bonding structure.
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