Invention Grant
- Patent Title: Method of deadlock detection and synchronization-aware optimizations on asynchronous architectures
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Application No.: US16933186Application Date: 2020-07-20
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Publication No.: US11429359B2Publication Date: 2022-08-30
- Inventor: Ahmed Mohammed ElShafiey Mohammed Eltantawy , Yaoqing Gao , Christopher Rodrigues , Lijuan Hai
- Applicant: Huawei Technologies Co., Ltd.
- Applicant Address: CN Shenzhen
- Assignee: Huawei Technologies Co., Ltd.
- Current Assignee: Huawei Technologies Co., Ltd.
- Current Assignee Address: CN Shenzhen
- Agency: Slater Matsil, LLP
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F8/41 ; G06F8/71 ; G06F9/52

Abstract:
A method for improving the performance of applications executed within asynchronous processor architectures. In an embodiment, a method for improving execution time of compiled synchronized source code on an asynchronous processor architecture includes receiving, by a processing system, synchronized source code comprising synchronization instructions to synchronize execution of the synchronized source code on different pipelines of the asynchronous processor architecture. The method also includes analyzing, by the processing system, the synchronized source code to determine whether the synchronized source code includes a broken code condition. The method also includes, after determining, by the processing system, that the synchronized source code does not include a broken code condition, outputting an optimized synchronized source code generated by performing a corrective action on the synchronized source code to correct a synchronization inaccuracy, inconsistency, or inefficiency in the synchronized source code.
Public/Granted literature
- US20210004213A1 Method of Deadlock Detection and Synchronization-Aware Optimizations on Asynchronous Architectures Public/Granted day:2021-01-07
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