- Patent Title: Defective bit line management in connection with a memory access
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Application No.: US17195579Application Date: 2021-03-08
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Publication No.: US11429469B2Publication Date: 2022-08-30
- Inventor: Ali Khakifirooz , Pranav Kalavade , Ravi H. Motwani , Chang Wan Ha
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F11/07
- IPC: G06F11/07 ; G11C16/34 ; G11C7/12 ; G11C16/14 ; G11C29/44

Abstract:
Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.
Public/Granted literature
- US20210193200A1 DEFECTIVE BIT LINE MANAGEMENT IN CONNECTION WITH A MEMORY ACCESS Public/Granted day:2021-06-24
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