Invention Grant
- Patent Title: Verification of programmable logic devices
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Application No.: US16844053Application Date: 2020-04-09
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Publication No.: US11443074B2Publication Date: 2022-09-13
- Inventor: Gennadiy Rozenberg , Naysen Robertson , Jhovel Louie Lopez
- Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Applicant Address: US TX Houston
- Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Current Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Current Assignee Address: US TX Houston
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: H04L9/32
- IPC: H04L9/32 ; G06F11/22 ; G06F15/78 ; G06F21/76 ; H03K19/17728 ; G06F21/44 ; H03K19/1776

Abstract:
A data processing system comprises a management processor, a programmable logic device (PLD) coupled to the management processor, and a machine-readable medium (MRM). The MRM comprises a PLD configuration image to configure the PLD with image-defined logic that comprises self-verification logic and an image-defined management interface to enable the management processor to communicate with the self-verification logic. The MRM also comprises a cryptographic signature based on the PLD configuration image. The MR also comprises PLD authentication instructions which, when executed by the management processor, cause the management processor to retrieve an address for the PLD configuration image from the PLD via the management interface, use the address to retrieve the PLD configuration image from the PLD via the management interface, retrieve the cryptographic signature from the PLD via the management interface, and use the cryptographic signature and a cryptographic key of a trusted entity to authenticate the PLD configuration image.
Public/Granted literature
- US20210319141A1 VERIFICATION OF PROGRAMMABLE LOGIC DEVICES Public/Granted day:2021-10-14
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