Verification of programmable logic devices

    公开(公告)号:US11443074B2

    公开(公告)日:2022-09-13

    申请号:US16844053

    申请日:2020-04-09

    Abstract: A data processing system comprises a management processor, a programmable logic device (PLD) coupled to the management processor, and a machine-readable medium (MRM). The MRM comprises a PLD configuration image to configure the PLD with image-defined logic that comprises self-verification logic and an image-defined management interface to enable the management processor to communicate with the self-verification logic. The MRM also comprises a cryptographic signature based on the PLD configuration image. The MR also comprises PLD authentication instructions which, when executed by the management processor, cause the management processor to retrieve an address for the PLD configuration image from the PLD via the management interface, use the address to retrieve the PLD configuration image from the PLD via the management interface, retrieve the cryptographic signature from the PLD via the management interface, and use the cryptographic signature and a cryptographic key of a trusted entity to authenticate the PLD configuration image.

    SUPPORT SERVICES FOR PROGRAMMABLE LOGIC DEVICES

    公开(公告)号:US20240255914A1

    公开(公告)日:2024-08-01

    申请号:US18159838

    申请日:2023-01-26

    CPC classification number: G05B19/05 G05B2219/13109

    Abstract: In some examples, a management controller includes a first interface through which the management controller is to provide a support service for any of a plurality of programmable logic devices in an electronic device. The management controller includes a controller processor to receive a code image to perform a programmable logic device update, where the code image comprises an identifier of a programmable logic device. In response to determining that the identifier corresponds to a given programmable logic device that is present in the electronic device, the management processor sets a multiplexer select value to control a multiplexer to connect the first interface of the management controller to the given programmable logic device. The management processor provides the code image to the given programmable logic device through the first interface and the multiplexer to update the given programmable logic device.

    VERIFICATION OF PROGRAMMABLE LOGIC DEVICES

    公开(公告)号:US20210319141A1

    公开(公告)日:2021-10-14

    申请号:US16844053

    申请日:2020-04-09

    Abstract: A data processing system comprises a management processor, a programmable logic device (PLD) coupled to the management processor, and a machine-readable medium (MRM). The MRM comprises a PLD configuration image to configure the PLD with image-defined logic that comprises self-verification logic and an image-defined management interface to enable the management processor to communicate with the self-verification logic. The MRM also comprises a cryptographic signature based on the PLD configuration image. The MR also comprises PLD authentication instructions which, when executed by the management processor, cause the management processor to retrieve an address for the PLD configuration image from the PLD via the management interface, use the address to retrieve the PLD configuration image from the PLD via the management interface, retrieve the cryptographic signature from the PLD via the management interface, and use the cryptographic signature and a cryptographic key of a trusted entity to authenticate the PLD configuration image.

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