Invention Grant
- Patent Title: Memory arrays and methods of forming memory arrays
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Application No.: US16739581Application Date: 2020-01-10
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Publication No.: US11444093B2Publication Date: 2022-09-13
- Inventor: Chandra Tiwari
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/11556
- IPC: H01L27/11556 ; H01L27/11582 ; G11C5/02 ; G11C5/06 ; G11C16/04

Abstract:
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. A horizontal pattern of operative memory-cell pillars extends through the insulative tiers and the conductive tiers in individual of the memory blocks. The operative memory-cell pillars have intrinsic compressive mechanical stress. At least one dummy structure in the individual memory blocks extends through at least upper of the insulative tiers and the conductive tiers. The at least one dummy structure is at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern. The at least one dummy structure has intrinsic tensile mechanical stress. Other embodiments, including methods, are disclosed.
Public/Granted literature
- US20210217761A1 Memory Arrays And Methods Of Forming Memory Arrays Public/Granted day:2021-07-15
Information query
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