Invention Grant
- Patent Title: Implementing fault tolerant page stripes on low density memory systems
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Application No.: US17079048Application Date: 2020-10-23
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Publication No.: US11449271B2Publication Date: 2022-09-20
- Inventor: Kishore Kumar Muchherla , Mark A. Helm , Giuseppina Puzzilli , Peter Feeley , Yifen Liu , Violante Moschiano , Akira Goda , Sampath K. Ratnam
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.
Public/Granted literature
- US20210200461A1 IMPLEMENTING FAULT TOLERANT PAGE STRIPES ON LOW DENSITY MEMORY SYSTEMS Public/Granted day:2021-07-01
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