公开(公告)号：US20240393980A1

公开(公告)日：2024-11-28

申请号：US18792881

申请日：2024-08-02

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Jiangli Zhu ,  Fangfang Zhu ,  Akira Goda ,  Lakshmi Kalpana Vakati ,  Vivek Shivhare ,  Dave Scott Ebsen ,  Sanjay Subbarao

IPC: G06F3/06

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.

公开(公告)号：US20240203516A1

公开(公告)日：2024-06-20

申请号：US18393284

申请日：2023-12-21

Applicant: Micron Technology, Inc.

Inventor： Aswin Thiruvengadam ,  Daniel L. Lowrance ,  Peter Feeley

IPC: G11C29/02 ,  G06F3/06 ,  G06F12/02 ,  G06F16/18 ,  G11C7/04 ,  G11C7/10 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G11C29/44

CPC classification number: G11C29/028 ,  G06F3/0652 ,  G06F12/0246 ,  G06F12/0292 ,  G06F16/1847 ,  G11C7/1072 ,  G11C16/10 ,  G11C16/32 ,  G11C16/3495 ,  G06F2212/7209 ,  G11C7/04 ,  G11C2029/4402

Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.

公开(公告)号：US12001721B2

公开(公告)日：2024-06-04

申请号：US17882355

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Lakshmi Kalpana Vakati ,  Dave Scott Ebsen ,  Peter Feeley ,  Sanjay Subbarao ,  Vivek Shivhare ,  Jiangli Zhu ,  Fangfang Zhu ,  Akira Goda

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0683

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

公开(公告)号：US20240161846A1

公开(公告)日：2024-05-16

申请号：US18389140

申请日：2023-11-13

Applicant: Micron Technology, Inc.

Inventor： Aswin Thiruvengadam ,  Daniel L. Lowrance ,  Peter Feeley

IPC: G11C29/02 ,  G06F12/02 ,  G11C16/10

CPC classification number: G11C29/028 ,  G06F12/0246 ,  G06F12/0292 ,  G11C16/10 ,  G11C2029/4402

Abstract: The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.

公开(公告)号：US20240126690A1

公开(公告)日：2024-04-18

申请号：US18395363

申请日：2023-12-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/06 ,  G06F12/0891

CPC classification number: G06F12/0253 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/00 ,  G06F12/0646 ,  G06F12/0891 ,  G11C11/5621

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

公开(公告)号：US11928347B2

公开(公告)日：2024-03-12

申请号：US18114967

申请日：2023-02-27

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mustafa N Kaynak ,  Peter Feeley ,  Sampath K Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Karl D Schuh ,  Jiangang Wu

IPC: G06F3/06 ,  G11C16/26

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/26

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.

公开(公告)号：US20240045616A1

公开(公告)日：2024-02-08

申请号：US17882355

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Lakshmi Kalpana Vakati ,  Dave Scott Ebsen ,  Peter Feeley ,  Sanjay Subbarao ,  Vivek Shivhare ,  Jiangli Zhu ,  Fangfang Zhu ,  Akira Goda

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0656 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0683

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

公开(公告)号：US11869605B2

公开(公告)日：2024-01-09

申请号：US17889863

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Sampath K Ratnam ,  Peter Feeley ,  Sivagnanam Parthasarathy

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3495 ,  G11C2207/2254

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a read operation on a block of the memory device by applying a read reference voltage to a selected wordline of the block and applying a pass-through voltage having a first value to a plurality of unselected wordlines of the block; detecting a read error in response to performing the read operation; and setting the pass-through voltage to a second value, wherein the second value is greater than the first value.

公开(公告)号：US20230282293A1

公开(公告)日：2023-09-07

申请号：US18110008

申请日：2023-02-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N Kaynak ,  Sampath K Ratnam ,  Shane Nowell ,  Peter Feeley ,  Sivagnanam Parthasarathy

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/32 ,  G11C16/26

CPC classification number: G11C16/3404 ,  G11C16/30 ,  G11C16/102 ,  G11C16/32 ,  G11C16/26

Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.

公开(公告)号：US11710527B2

公开(公告)日：2023-07-25

申请号：US17868685

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Qisong Lin ,  Shane Nowell ,  Mustafa N. Kaynak

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C29/00 ,  G06F11/07 ,  G11C16/26 ,  G06F3/06 ,  G11C16/04

CPC classification number: G11C16/34 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/84 ,  G11C16/0483 ,  G11C2207/229 ,  G11C2207/2272 ,  G11C2207/2281

Abstract: A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.