-
公开(公告)号：US12067290B2
公开(公告)日：2024-08-20
申请号：US17591406
申请日：2022-02-02
发明人： Kishore Kumar Muchherla , Violante Moschiano , Akira Goda , Jeffrey S. McNeil , Jung Sheng Hoei , Sivagnanam Parthasarathy , James Fitzpatrick , Patrick R. Khayat
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679
摘要： Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.
-
公开(公告)号：US20240203501A1
公开(公告)日：2024-06-20
申请号：US18404282
申请日：2024-01-04
IPC分类号： G11C16/10 , G06F12/0802 , G11C11/56 , G11C16/04
CPC分类号： G11C16/10 , G06F12/0802 , G11C16/0483 , G06F2212/60 , G06F2212/72 , G11C11/56
摘要： Control logic in a memory device initiates a programming operation to program a set of memory cells of the memory device to a target programming level of a set of programming levels. During execution of the programming operation, a programming status associated with the set of memory cells. In response to determining the programming status satisfies a condition, causing a release of a set of data associated with the programming operation from a cache register.
-
公开(公告)号：US11842774B2
公开(公告)日：2023-12-12
申请号：US17583537
申请日：2022-01-25
CPC分类号： G11C16/28 , G06F11/1008 , G11C13/004 , G11C16/107
摘要： Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.
-
公开(公告)号：US11776633B2
公开(公告)日：2023-10-03
申请号：US17120337
申请日：2020-12-14
IPC分类号： G11C8/00 , G11C16/26 , G11C16/10 , G11C16/34 , G11C16/04 , G11C5/14 , G11C11/4074 , G11C7/04 , G11C11/56
CPC分类号： G11C16/26 , G11C5/145 , G11C5/147 , G11C7/04 , G11C11/4074 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459
摘要： Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.
-
公开(公告)号：US20230298680A1
公开(公告)日：2023-09-21
申请号：US18110489
申请日：2023-02-16
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/20
摘要： Memories might include a controller configured to cause the memory to prepare a first plurality of memory cells of a block of memory cells for programming from an initialization state of the block of memory cells, program the first data to the first plurality of memory cells, and, in response to receiving a write command associated with a second address corresponding to the block of memory cells and with second data before successfully verifying programming of the first data to the first plurality of memory cells, prepare a second plurality of memory cells of the block of memory cells corresponding to the second address for programming without returning the block of memory cells to the initialization state after programming the first data to the first plurality of memory cells.
-
公开(公告)号：US20230214133A1
公开(公告)日：2023-07-06
申请号：US18090449
申请日：2022-12-28
发明人： Kishore Kumar Muchherla , Akira Goda , Jeffrey S. McNeil , Niccolo' Righetti , Silvia Beltrami , Violante Moschiano , Ugo Russo
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0679 , G06F3/0659
摘要： A memory device comprises an array of memory cells organized into a plurality of wordlines, and a processing device to perform processing operations that receive a program command specifying a memory unit and data comprising first received data, where the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines. The processing operations also program the specified data to the memory unit by programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, and programming the first data pattern to the first retired boundary wordline.
-
公开(公告)号：US20230206992A1
公开(公告)日：2023-06-29
申请号：US18083077
申请日：2022-12-16
发明人： Kishore Kumar Muchherla , Junwyn A. Lacsao , Jeffrey S. McNeil , Violante Moschiano , Paing Z. Htet , Sead Zildzic , Eric N. Lee
IPC分类号： G11C11/4091 , G11C11/4099 , G11C11/4093
CPC分类号： G11C11/4091 , G11C11/4093 , G11C11/4099
摘要： Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.
-
公开(公告)号：US20230197163A1
公开(公告)日：2023-06-22
申请号：US18076488
申请日：2022-12-07
发明人： Jeffrey S. McNeil , Kishore Kumar Muchherla , Sead Zildzic , Akira Goda , Jonathan S. Parry , Violante Moschiano
CPC分类号： G11C16/102 , G11C16/08 , G11C16/28
摘要： A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.
-
公开(公告)号：US20230099349A1
公开(公告)日：2023-03-30
申请号：US18073402
申请日：2022-12-01
摘要： An apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.
-
公开(公告)号：US20230065421A1
公开(公告)日：2023-03-02
申请号：US17675526
申请日：2022-02-18
IPC分类号： G11C16/10 , G11C16/04 , G06F12/0802
摘要： Control logic in a memory device initiates an express programming operation to program the set of memory cells to a target programming level of a set of programming levels. A set of data associated with the express programming operation is stored in a cache register. At a first time during the execution of the express programming operation, a prediction operation is executed to determine a prediction result corresponding to a programming status of the set of memory cells. The prediction result is compared to a threshold level to determine whether a condition is satisfied. The release of the set of data from the cache register is caused in response to satisfying the condition.
-
-
-
-
-
-
-
-
-
搜索结果
222 条记录 (耗时 0.032 秒)
