Invention Grant
- Patent Title: Methods and arrangements to accelerate array searches
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Application No.: US15941381Application Date: 2018-03-30
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Publication No.: US11456972B2Publication Date: 2022-09-27
- Inventor: Keith Underwood , Karl Brummel , John Greth
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: KDB Firm PLLC
- Main IPC: H04L49/901
- IPC: H04L49/901 ; H04L45/745 ; H04L49/35 ; H04L67/568 ; H04L49/9047 ; H04L69/04

Abstract:
Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.
Public/Granted literature
- US20190044890A1 METHODS AND ARRANGEMENTS TO ACCELERATE ARRAY SEARCHES Public/Granted day:2019-02-07
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