公开(公告)号：US11456972B2

公开(公告)日：2022-09-27

申请号：US15941381

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Keith Underwood ,  Karl Brummel ,  John Greth

IPC: H04L49/901 ,  H04L45/745 ,  H04L49/35 ,  H04L67/568 ,  H04L49/9047 ,  H04L69/04

Abstract: Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

公开(公告)号：US11916800B2

公开(公告)日：2024-02-27

申请号：US16912553

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： David Arditti Ilitzky ,  John Greth ,  Robert Southworth ,  Karl S. Papadantonakis ,  Bongjin Jung ,  Arvind Srinivasan

IPC: H04L47/283 ,  H04L43/087 ,  H04L43/16 ,  H04L49/00 ,  H04L47/125 ,  H04L49/25 ,  H04L49/90 ,  H04L47/62

CPC classification number: H04L47/283 ,  H04L43/087 ,  H04L43/16 ,  H04L47/125 ,  H04L47/6205 ,  H04L49/25 ,  H04L49/3063 ,  H04L49/9042

Abstract: Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer. In some examples, a fetch scheduler is used to adapt an amount of interface overspeed to reduce packet fetching latency while attempting to prevent fabric saturation based on a switch fabric load level, wherein the fetch scheduler is to control the jitter threshold level for the buffer by forcing a jitter threshold level based on switch fabric load level and latency profile of the switch fabric.

公开(公告)号：US11722438B2

公开(公告)日：2023-08-08

申请号：US16546993

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： John Greth ,  Arvind Srinivasan ,  Robert Southworth ,  David Arditti Ilitzky ,  Bongjin Jung ,  Gaspar Mora Porta

IPC: H04L49/00 ,  H04L49/25 ,  H04L9/40 ,  H04L69/22 ,  H04L41/0896 ,  H04L49/90

CPC classification number: H04L49/3045 ,  H04L41/0896 ,  H04L49/257 ,  H04L49/9042 ,  H04L63/101 ,  H04L69/22

Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.

公开(公告)号：US20190044890A1

公开(公告)日：2019-02-07

申请号：US15941381

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Keith Underwood ,  Karl Brummel ,  John Greth

IPC: H04L12/879 ,  H04L29/08

Abstract: Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.