Insulation layer arrangement for magnetic tunnel junction device
Abstract:
Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.
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