Invention Grant
- Patent Title: Vertical decoder
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Application No.: US17193227Application Date: 2021-03-05
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Publication No.: US11468930B2Publication Date: 2022-10-11
- Inventor: Andrea Redaelli , Fabio Pellizzer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G11C8/10
- IPC: G11C8/10 ; G11C5/06 ; G11C5/02

Abstract:
Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.
Public/Granted literature
- US20210264956A1 VERTICAL DECODER Public/Granted day:2021-08-26
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