Invention Grant
- Patent Title: System-on-chip including network for debugging
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Application No.: US16556905Application Date: 2019-08-30
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Publication No.: US11470018B2Publication Date: 2022-10-11
- Inventor: Kyuseung Han , Sukho Lee , Jae-Jin Lee , Sang Pil Kim , Young Hwan Bae , Kyung Jin Byun
- Applicant: Electronics and Telecommunications Research Institute
- Applicant Address: KR Daejeon
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR Daejeon
- Agency: Rabin & Berdo, P.C.
- Priority: KR10-2018-0109862 20180913
- Main IPC: H04L49/109
- IPC: H04L49/109 ; H04L12/42 ; G06F11/07

Abstract:
Provided is a system-on-chip. A central controller is configured to, in response to a request from a host, generate a first signal for requesting error information related to an error from a design of an IP. A local controller is configured to generate a second signal including the error information of the target IP if the request from the host is determined to be for the target IP based on the first signal.
Public/Granted literature
- US20200092226A1 SYSTEM-ON-CHIP INCLUDING NETWORK FOR DEBUGGING Public/Granted day:2020-03-19
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