公开(公告)号：US12088504B2

公开(公告)日：2024-09-10

申请号：US18214665

申请日：2023-06-27

申请人： Barefoot Networks, Inc.

发明人： Yi Li ,  Michael Feng ,  Anurag Agrawal ,  Jeongkeun Lee ,  Changhoon Kim ,  Remy Chang

IPC分类号： H04L47/625 ,  H04L12/18 ,  H04L41/142 ,  H04L43/0882 ,  H04L43/16 ,  H04L45/00 ,  H04L45/24 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/32 ,  H04L47/62 ,  H04L47/628 ,  H04L49/00 ,  H04L49/101 ,  H04L49/109 ,  H04L49/90 ,  H04L69/22

CPC分类号： H04L47/6255 ,  H04L41/142 ,  H04L43/0882 ,  H04L43/16 ,  H04L45/245 ,  H04L45/72 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/32 ,  H04L47/62 ,  H04L47/628 ,  H04L49/109 ,  H04L49/3063 ,  H04L49/90 ,  H04L69/22 ,  H04L12/1886 ,  H04L49/101

摘要： Some embodiments provide a method for an ingress packet processing pipeline of a network forwarding integrated circuit (IC). The ingress packet processing pipeline is for receiving packets from a port of the network forwarding IC and processing the packets to assign different packets to different queues of a traffic management unit of the network forwarding IC. The method receives state data from the traffic management unit. The method stores the state data in a stateful table. The method assigns a particular packet to a particular queue based on the state data received from the traffic management unit and stored in the stateful table.

公开(公告)号：US12047933B2

公开(公告)日：2024-07-23

申请号：US18301651

申请日：2023-04-17

申请人： CommScope Technologies LLC

发明人： Vedat Eyuboglu ,  Arthur J. Barabell

IPC分类号： H04W72/12 ,  H04B7/04 ,  H04B7/06 ,  H04J11/00 ,  H04L1/00 ,  H04L1/1812 ,  H04L5/00 ,  H04L27/34 ,  H04L49/109 ,  H04L49/25 ,  H04W72/54 ,  H04W84/12 ,  H04W88/12 ,  H04W88/16

CPC分类号： H04W72/12 ,  H04B7/04 ,  H04B7/0626 ,  H04J11/00 ,  H04L1/0036 ,  H04L1/1812 ,  H04L5/0023 ,  H04L5/005 ,  H04L27/34 ,  H04L49/109 ,  H04L49/25 ,  H04W72/54 ,  H04L5/0055 ,  H04L5/0073 ,  H04W84/12 ,  H04W88/12 ,  H04W88/16

摘要： A communication system includes remote units to exchange RF signals with mobile devices, at least some of the RF signals comprising information destined for, or originating from, a mobile device. The communication system also includes at least one controller or controller resource communicatively coupled to an external network and configured to assign airlink resources to the user equipment. The at least one controller or controller resource is separated from the remote units by an intermediate network comprising a switched Ethernet network over which data corresponding to the information is carried between the at least one controller or controller resource and the remote units. Two or more of the remote units are configured to belong to the same communication cell. The at least one controller or controller resource is configured to assign two or more of the user equipment in the same communication cell to simultaneously use a same airlink resource.

公开(公告)号：US20240223513A1

公开(公告)日：2024-07-04

申请号：US18089775

申请日：2022-12-28

申请人： XILINX, INC.

发明人： Ahmad R. ANSARI ,  John O'DWYER

IPC分类号： H04L49/102 ,  H04L49/109 ,  H04L49/15

CPC分类号： H04L49/102 ,  H04L49/109 ,  H04L49/15

摘要： Embodiments herein describe an integrated circuit (IC) which includes a global ring that interconnects multiple local rings distributed throughout the IC. In one embodiment, the global ring is connected to the local rings using respective switches. The global ring (and the switches) interconnect the local rings so that a node coupled to one of the local rings can communicate with a node connected to another local ring.

公开(公告)号：US11962462B2

公开(公告)日：2024-04-16

申请号：US18321516

申请日：2023-05-22

申请人： STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

发明人： Nicolas Anquet ,  Loic Pallardy

IPC分类号： H04L41/0803 ,  G06F15/173 ,  G06F15/177 ,  H04L41/0813 ,  H04L49/109 ,  G06F21/85

CPC分类号： H04L41/0813 ,  G06F15/17306 ,  G06F15/177 ,  H04L41/0803 ,  H04L49/109 ,  G06F21/85

摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

公开(公告)号：US20230412515A1

公开(公告)日：2023-12-21

申请号：US18457058

申请日：2023-08-28

申请人： Avago Technologies International Sales Pte. Limited

发明人： Sachin Prabhakarrao Kadu

IPC分类号： H04L47/2483 ,  H04L45/24 ,  H04L47/6275 ,  H04L49/109

CPC分类号： H04L47/2483 ,  H04L45/24 ,  H04L47/6275 ,  H04L49/109

摘要： A semiconductor chip for implementing aggregated flow detection and management includes a number of pipes, where each pipe is coupled to a portion of ports on the semiconductor chip that are to receive data packets. A logic is coupled to the pipes and is used to detect and manage an elephant flow. The elephant flow-detection and management logic includes a flow table and a byte counter.

公开(公告)号：US20230370392A1

公开(公告)日：2023-11-16

申请号：US17663376

申请日：2022-05-13

申请人： Xilinx, Inc.

发明人： Krishnan Srinivasan ,  Sagheer Ahmad ,  Ygal Arbel ,  Aman Gupta

IPC分类号： H04L49/109

CPC分类号： H04L49/109

摘要： An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.

公开(公告)号：US11817944B2

公开(公告)日：2023-11-14

申请号：US17702493

申请日：2022-03-23

申请人： Black Sesame Technologies Inc.

发明人： Jianfeng Zhang ,  Long Zhang ,  Weifu Chen

IPC分类号： H04J3/06 ,  H04L49/109 ,  H04L67/12

CPC分类号： H04J3/0635 ,  H04L49/109 ,  H04L67/12

摘要： A time synchronization method, apparatus, domain controller, and storage medium are disclosed. The domain controller is mounted in a vehicle and includes a number of SoCs and micro control units. The SoCs and micro control units are respectively, communicatively connected through the controller area network bus and respectively connected to the switch via Ethernet. The switch has external Ethernet interfaces. A main SoC in the number of SoCs has external UART/PPS interfaces and the micro control units have external FlexRay interfaces. The time synchronization method of the domain controller includes any one of the steps of receiving a time service from an external device through the UART/PPS interfaces, receiving a time service from the external device through the switch over the Ethernet interface, or receiving a time service from the external device through the FlexRay interface under a normal operation phase of the vehicle.

公开(公告)号：US20230283490A1

公开(公告)日：2023-09-07

申请号：US18176568

申请日：2023-03-01

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Xiaodong XU

IPC分类号： H04L12/12 ,  H04L41/0681 ,  H04L49/109

CPC分类号： H04L12/12 ,  H04L41/0681 ,  H04L49/109

摘要： The technology of this application relates to a network chip management method. In the method, resource requirement information of a current network for a network chip is determined based on one or more of port information, configuration information, and traffic information of the network chip. A target operating frequency of the network chip is determined based on the resource requirement information. The network chip is controlled to operate at the target operating frequency. In this way, an operating frequency of the network chip adapts to the current network, so that power consumption of the network chip can be dynamically adjusted based on the current network, and the power consumption of the network chip is reduced while a network requirement is met.

公开(公告)号：US11750511B2

公开(公告)日：2023-09-05

申请号：US17699427

申请日：2022-03-21

申请人： Sean Iwasaki

发明人： Sean Iwasaki

IPC分类号： H04L45/60 ,  H04L49/109 ,  H04L49/00 ,  H04L49/35 ,  G02B6/42 ,  G02B6/44

CPC分类号： H04L45/60 ,  H04L49/109 ,  H04L49/30 ,  H04L49/355

摘要： The present subject matter relates to methods, circuitry and equipment providing a multi-functional, cost effective, media independent, open platform device for communication services using differential signaling interfaces. The methods, circuitry and equipment comprise a plurality of input amplifiers, output amplifiers, and retimers. A non-blocking cross-point switch may be used to switch any differential signals from the cross-point switch input to output. The device aggregates communication services from a plurality of lower service capacity connectors and interfaces to a single higher capacity connector and interfaces. The device can establish a demarcation point with a single device capable of supporting any communication services, any physical media interfaces, from any location.

公开(公告)号：US11704270B2

公开(公告)日：2023-07-18

申请号：US17305680

申请日：2021-07-13

申请人： Graphcore Limited

发明人： Simon Knowles ,  Hachem Yassine

IPC分类号： G06F13/40 ,  H04L49/109

CPC分类号： G06F13/4022 ,  G06F13/4013 ,  G06F13/4063 ,  H04L49/109 ,  G06F2213/0038

摘要： A network comprising interconnected first and second processors, each processor comprising one or more of: multiple processing units arranged on a chip configured to execute program code; an on-chip interconnect comprising groups of exchange paths connected to receive data from corresponding groups of the processing units; external interfaces configured to communicate data off-chip as packets, each having a destination address, external interfaces of the first and second processors being connected by an external link; multiple exchange blocks, each connected to groups of the exchange paths; a routing bus configured to route packets between the exchange blocks and the external interfaces. Processing units of the first processor generate off-chip packets such that the group of processing units serviced by the first exchange block on the first processor address off-chip packets to the group of processing units on the second processor serviced by the corresponding first exchange block of the second processor.