- Patent Title: Stacked silicon package assembly having vertical thermal management
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Application No.: US16718868Application Date: 2019-12-18
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Publication No.: US11488936B2Publication Date: 2022-11-01
- Inventor: Gamal Refai-Ahmed , Suresh Ramalingam , Jaspreet Singh Gandhi , Cheang-Whang Chang
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/367 ; H01L23/04 ; H01L23/31

Abstract:
A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.
Public/Granted literature
- US20210193620A1 STACKED SILICON PACKAGE ASSEMBLY HAVING VERTICAL THERMAL MANAGEMENT Public/Granted day:2021-06-24
Information query
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