中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.013 seconds)

    Method of testing a semiconductor structure
    3.
    发明授权
    Method of testing a semiconductor structure 有权
    测试半导体结构的方法

    公开(公告)号：US08810269B2

    公开(公告)日：2014-08-19

    申请号：US13630215

    申请日：2012-09-28

    Applicant: Xilinx, Inc.

    Inventor： Yuqing Gong ,  Henley Liu ,  Myongseob Kim ,  Suresh P. Parameswaran ,  Cheang-Whang Chang ,  Boon Y. Ang

    IPC: G01R31/3187

    CPC classification number: G01R31/31926 ,  G01R31/2812 ,  G01R31/31717 ,  G01R31/31723 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

    Abstract translation: 集成电路（IC）包括路由电路，其包括在IC的路由层中的多个信号线段以及耦合到路由电路的多个微突点接触。 IC包括耦合到多个信号线段的相应子集的多个测试电路。 每个测试电路被配置为连接相应子集中的微凸块触点以形成第一组和第二组菊花链。 每个测试电路被配置为测试用于开路的第一和第二组菊花链，并测试第一组和第二组菊花链之间的短路。 每个测试电路被配置为确定检测到的开路的位置并确定检测到的短路的位置。

    METHOD AND DESIGN OF LOW SHEET RESISTANCE MEOL RESISTORS
    5.
    发明申请
    METHOD AND DESIGN OF LOW SHEET RESISTANCE MEOL RESISTORS 审中-公开
    低电阻电阻器的方法和设计

    公开(公告)号：US20170012041A1

    公开(公告)日：2017-01-12

    申请号：US14792847

    申请日：2015-07-07

    Applicant: Xilinx, Inc.

    Inventor： Nui Chong ,  Jae-Gyung Ahn ,  Ping-Chin Yeh ,  Cheang-Whang Chang

    IPC: H01L27/07 ,  H01L21/76 ,  H01L21/283 ,  H01L49/02 ,  H01L27/02

    CPC classification number: H01L27/0738 ,  H01L21/283 ,  H01L21/76 ,  H01L23/5228 ,  H01L27/0207 ,  H01L27/0629 ,  H01L28/24

    Abstract: An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.

    Abstract translation: 集成电路结构包括：半导体衬底; 在半导体衬底中的浅沟槽隔离（STI）区域; 形成在半导体衬底上的一个或多个有源器件; 以及具有设置在所述STI区域上方的多个电阻器的电阻器阵列; 其中所述电阻器阵列包括用于与所述一个或多个有源器件互连的一个或多个互连接触层的一部分。

    STACKED SILICON PACKAGE ASSEMBLY HAVING VERTICAL THERMAL MANAGEMENT
    6.
    发明申请
    STACKED SILICON PACKAGE ASSEMBLY HAVING VERTICAL THERMAL MANAGEMENT 有权

    公开(公告)号：US20210193620A1

    公开(公告)日：2021-06-24

    申请号：US16718868

    申请日：2019-12-18

    Applicant: Xilinx, Inc.

    Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

    IPC: H01L25/065 ,  H01L23/04 ,  H01L23/31 ,  H01L23/367

    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

    IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC
    9.
    发明申请
    IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC 审中-公开
    IC中的In-DIE晶体管特性

    公开(公告)号：US20160097805A1

    公开(公告)日：2016-04-07

    申请号：US14505240

    申请日：2014-10-02

    Applicant: Xilinx, Inc

    Inventor： Ping-Chin Yeh ,  John K. Jennings ,  Rhesa Nathanael ,  Nui Chong ,  Cheang-Whang Chang ,  Daniel Y. Chung

    IPC: G01R31/28

    CPC classification number: G01R31/2851 ,  G01R31/2837 ,  G01R31/2843 ,  G01R31/3167

    Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

    Abstract translation: 在示例实现中，集成电路（IC）包括：设置在IC的管芯上的多个位置中的多个晶体管; 耦合到所述多个晶体管中的每一个的端子的导体; 耦合到所述导体的数模转换器（DAC），以响应于数字输入将电压信号驱动到所述多个晶体管; 以及耦合到所述导体的至少一部分的模数转换器（ADC），以响应于所述电压信号而响应于在所述多个晶体管中感应的电流信号而生成样本，所述样本至少指示 一个静电特性用于多个晶体管。

    METHOD OF TESTING A SEMICONDUCTOR STRUCTURE
    10.
    发明申请
    METHOD OF TESTING A SEMICONDUCTOR STRUCTURE 有权
    测试半导体结构的方法

    公开(公告)号：US20140091819A1

    公开(公告)日：2014-04-03

    申请号：US13630215

    申请日：2012-09-28

    Applicant: XILINX, INC.

    Inventor： Yuqing Gong ,  Henley Liu ,  Myongseob Kim ,  Suresh P. Parameswaran ,  Cheang-Whang Chang ,  Boon Y. Ang

    IPC: G01R31/3187

    CPC classification number: G01R31/31926 ,  G01R31/2812 ,  G01R31/31717 ,  G01R31/31723 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

    Abstract translation: 集成电路（IC）包括路由电路，其包括在IC的路由层中的多个信号线段以及耦合到路由电路的多个微突点接触。 IC包括耦合到多个信号线段的相应子集的多个测试电路。 每个测试电路被配置为连接相应子集中的微凸块触点以形成第一组和第二组菊花链。 每个测试电路被配置为测试用于开路的第一和第二组菊花链，并测试第一组和第二组菊花链之间的短路。 每个测试电路被配置为确定检测到的开路的位置并确定检测到的短路的位置。

Patent Agency Ranking