Invention Grant
- Patent Title: Method of cointegrating semiconductor structures for different voltage transistors
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Application No.: US17127424Application Date: 2020-12-18
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Publication No.: US11488954B2Publication Date: 2022-11-01
- Inventor: Eugenio Dentoni Litta , Alessio Spessot
- Applicant: IMEC vzw
- Applicant Address: BE Leuven
- Assignee: IMEC vzw
- Current Assignee: IMEC vzw
- Current Assignee Address: BE Leuven
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Priority: EP19218175 20191219
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L21/8234 ; H01L27/112 ; H01L27/11546 ; H01L21/467

Abstract:
The disclosed technology relates generally to semiconductor devices and manufacturing methods thereof, and more particularly to field-effect transistors operating at different voltages and methods for integrating the same. In one aspect, a method of fabricating a semiconductor device comprises: a) providing a substrate and a first hardmask; b) next, providing a second hardmask over a first region of the first hardmask; c) next, forming a first set of hardmask fins in a second region of the first hardmask; d) next, masking the second region; e) next, providing a set of photoresist fins on the second hardmask; f) next, patterning the second hardmask and the first region by using the photoresist fins as a mask; g) next, forming a first set of semiconductor fins of a first height by etching the substrate; h) next, removing the mask provided in step d; i) next, forming a second set of semiconductor fins of a second height in the second region and extending the height of the first set of semiconductor fins to a third height in the first region, by etching the substrate by using the first and second sets of hardmask fins as masks.
Public/Granted literature
- US20210202480A1 COINTEGRATED SEMICONDUCTOR STRUCTURES FOR DIFFERENT VOLTAGE TRANSISTORS Public/Granted day:2021-07-01
Information query
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