公开(公告)号：US20250098336A1

公开(公告)日：2025-03-20

申请号：US18882961

申请日：2024-09-12

Applicant: IMEC VZW ,  UNIVERSITEIT HASSELT

Inventor： Tom BORGERS ,  Jonathan GOVAERTS

IPC: H01L31/0443 ,  H01L31/05

Abstract: A photovoltaic module includes at least one string of solar cells wherein the solar cells are electrically connected in series using a plurality of connecting elements, wherein each connecting element electrically connects a frontside of one of the solar cells of the at least one string with a backside of the neighboring solar cell of the at least one string; a weave of electrically insulating yarns on which the solar cells are positioned; at least one electronic device comprising a first terminal, and a second terminal, wherein the at least one electronic device is fixed to the weave and wherein the first terminal, and the second terminal are respectively electrically connected with the connecting elements at the backsides of neighboring solar cells of the at least one string.

公开(公告)号：US12249970B2

公开(公告)日：2025-03-11

申请号：US17280105

申请日：2019-09-24

Applicant: UNIVERSITEIT GENT ,  IMEC VZW

Inventor： Guy Torfs ,  Michiel Verplaetse

IPC: H03H17/02 ,  H03H15/02 ,  H03H17/06

Abstract: A filter includes cascaded building blocks, for filtering an incoming signal. Each building block has first and second delay elements. A first scaling device is between an input node of the first delay element and an output node of the second delay element, and a second scaling device is between an output node of the first delay element and an input node of the second delay element. The building block has a cross scaling device between the output nodes of the first delay element and of the second delay element, and/or between the input nodes of the first delay element and of the second delay element. The building block is configured such that, in operation, incoming signals at the input node and output node of the second delay element are summed together.

公开(公告)号：US12237371B2

公开(公告)日：2025-02-25

申请号：US17476747

申请日：2021-09-16

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens ,  Eugenio Dentoni Litta

IPC: H01L29/06 ,  H01L29/786

Abstract: A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.

公开(公告)号：US20250048690A1

公开(公告)日：2025-02-06

申请号：US18715354

申请日：2021-12-02

Applicant: IMEC VZW ,  Huawei Technologies Co., Ltd.

Inventor： Bilal CHEHAB ,  Krishna Kumar BHUWALKA ,  Julien RYCKAERT

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: The disclosure relates to a CFET device (100) comprising: a bottom FET device (130) and a top FET device (140) stacked on top of the bottom FET device (130), the bottom FET device (130) comprising a bottom channel nanostructure (132) and a bottom gate electrode (134) comprising a side gate portion (134a) arranged along a first side surface (132a) of the bottom channel nano structure, and the top FET device (140) comprising a top channel nanosheet (142) and a top gate electrode (144) configured to define a tri-gate with respect to the top channel nanosheet and comprising a side gate portion (144b) arranged along a second side surface (142b) of the top channel nanosheet, wherein the side gate portion (134a) of the bottom gate electrode (134) defines a via contact portion protruding outside the top gate electrode (144) and the first side surface (142a) of the top channel nanosheet (142); and atop gate contact via (146) for coupling the top gate electrode (144) to a first conductive line (124) over the top FET device (140) and a bottom gate contact via (136) for coupling the via contact portion (134a) of the bottom gate electrode (134) to a second conductive line (128) over the top FET device (140).

公开(公告)号：US12216057B2

公开(公告)日：2025-02-04

申请号：US17371609

申请日：2021-07-09

Applicant: IMEC VZW

Inventor： Thomas Nuytten ,  Janusz Bogdanowicz

IPC: G01N21/65 ,  H01L21/66

Abstract: A method and apparatus are provided for a spectroscopic measurement for determining a lateral recess depth in the sidewall of a microstructure. The structure is formed on a larger substrate with the sidewall in an upright position relative to the substrate, and the recess extends essentially parallel to the substrate. The recess may be an etch depth obtained by etching a first layer relative to two adjacent layers, the layers oriented parallel to the substrate, the etch process progressing inward from the sidewall. An incident energy beam falling on the structure generates a spectroscopic response captured and processed respectively by a detector and a processing unit. The response comprises one or more peaks related to the material or materials of the substrate and the structure. According to the method, a parameter is derived from said one or more peaks, that is representative of the lateral recess depth.

公开(公告)号：US20250012895A1

公开(公告)日：2025-01-09

申请号：US18763273

申请日：2024-07-03

Applicant: IMEC VZW

Inventor： Hamed Javadi ,  Hichem Sahli ,  Andre Bourdoux

IPC: G01S7/41 ,  G01S13/90

Abstract: A system includes at least two photovoltaic modules each comprising a respective module area being substantially perpendicular to the thickness of the corresponding photovoltaic module. Each of the at least two module areas comprises at least one of two first sides being substantially perpendicular to the thickness of the corresponding photovoltaic module and/or two second sides being substantially perpendicular to the thickness of the corresponding photovoltaic module. In this context, the at least two module areas are arranged in a substantially parallel manner with respect to each other and are shifted with respect to each other in an extension direction of the system. In addition to this, the at least two module areas are arranged in a staggering or alternating or ascending or descending manner with respect to an extension plane in the extension direction of t

公开(公告)号：US12191880B2

公开(公告)日：2025-01-07

申请号：US18083823

申请日：2022-12-19

Applicant: IMEC VZW

Inventor： Ewout Martens ,  Jan Craninckx

IPC: H03M1/16 ,  H03M1/12 ,  H03M1/56

Abstract: A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.

公开(公告)号：US12188895B2

公开(公告)日：2025-01-07

申请号：US17692717

申请日：2022-03-11

Applicant: IMEC VZW

Inventor： David Barge ,  Bert Du Bois ,  Simone Severi ,  Ashesh Ray Chaudhuri

IPC: H01L21/00 ,  G01N27/414

Abstract: A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) patterning the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.

公开(公告)号：US20240404273A1

公开(公告)日：2024-12-05

申请号：US18796196

申请日：2024-08-06

Applicant: Imec vzw ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Ruoyu Feng ,  Andre Bourdoux ,  Hichem Sahli ,  Sofie Pollin

IPC: G06V20/00 ,  G01S13/72 ,  G01S13/89 ,  G06T7/277

Abstract: A method is provided for indoor multipath ghosts recognition for a multiple-input-multiple-output radar with collocated antennas. The method includes the step of generating a two-dimensional Range-Doppler map for N number of consecutive radar data frames. The method further includes the step of applying a temporal clustering algorithm to the N number of consecutive radar data frames. Moreover, the method includes the step of applying a linear pattern extraction algorithm on the two-dimensional Range-Doppler map. In this context, the two-dimensional Range-Doppler map comprises detections from at least one target, at least one first-order ghost, and at least one second-order ghost with respect to one wall reflector.

公开(公告)号：US12154979B2

公开(公告)日：2024-11-26

申请号：US17496186

申请日：2021-10-07

Applicant: IMEC VZW

Inventor： Aryan Afzalian

IPC: H01L29/772 ,  H03K17/687

Abstract: A field-effect transistor and a method for controlling such is provided herein. The field-effect transistor includes a source terminal and a drain terminal arranged on a first side of a semiconductor layer and a single gate arranged on a second side of the semiconductor layer opposite the first side. The gate and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the gate and the drain terminal are arranged to overlap with a second common region of the semiconductor layer.