- 专利标题: Combining voltage ramps to create linear voltage ramp
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申请号: US17248873申请日: 2021-02-11
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公开(公告)号: US11496121B2公开(公告)日: 2022-11-08
- 发明人: Joseph H. Colles , Steven E. Rosenbaum
- 申请人: Silanna Asia Pte Ltd
- 申请人地址: SG Singapore
- 专利权人: Silanna Asia Pte Ltd
- 当前专利权人: Silanna Asia Pte Ltd
- 当前专利权人地址: SG Singapore
- 代理机构: MLO, a professional corp.
- 主分类号: H03K4/50
- IPC分类号: H03K4/50 ; H03K7/08
摘要:
An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.
公开/授权文献
- US20210167763A1 COMBINING VOLTAGE RAMPS TO CREATE LINEAR VOLTAGE RAMP 公开/授权日:2021-06-03
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