Invention Grant
- Patent Title: Multi-chip packaging of silicon photonics
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Application No.: US17070601Application Date: 2020-10-14
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Publication No.: US11500153B2Publication Date: 2022-11-15
- Inventor: Roy Edward Meade , Chong Zhang , Haiwei Lu , Chen Li
- Applicant: Ayar Labs, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Ayar Labs, Inc.
- Current Assignee: Ayar Labs, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Penilla IP, APC
- Main IPC: G02B6/122
- IPC: G02B6/122 ; G02B6/12

Abstract:
A multi-chip package assembly includes a substrate, a first semiconductor chip attached to the substrate, and a second semiconductor chip attached to the substrate, such that a portion of the second semiconductor chip overhangs an edge of the substrate. A first v-groove array for receiving a plurality of optical fibers is present within the portion of the second semiconductor chip that overhangs the edge of the substrate. An optical fiber assembly including the plurality of optical fibers is positioned and secured within the first v-groove array of the second semiconductor chip. The optical fiber assembly includes a second v-groove array configured to align the plurality of optical fibers to the first v-groove array of the second semiconductor chip. An end of each of the plurality of optical fibers is exposed for optical coupling within an optical fiber connector located at a distal end of the optical fiber assembly.
Public/Granted literature
- US20210109284A1 Multi-Chip Packaging of Silicon Photonics Public/Granted day:2021-04-15
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