Invention Grant
- Patent Title: Electro-migration barrier for interconnect
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Application No.: US17104534Application Date: 2020-11-25
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Publication No.: US11515255B2Publication Date: 2022-11-29
- Inventor: Su-Jen Sung , Chih-Chiang Chang , Chia-Ho Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/768

Abstract:
The present disclosure relates to an integrated circuit having a conductive interconnect disposed on a dielectric over a substrate. A first liner is arranged along an upper surface of the conductive interconnect. A barrier layer is arranged along a lower surface of the conductive interconnect and contacts an upper surface of the dielectric. The barrier layer and the first liner surround the conductive interconnect. A second liner is located over the first liner and has a lower surface contacting the upper surface of the dielectric.
Public/Granted literature
- US20210082831A1 ELECTRO-MIGRATION BARRIER FOR INTERCONNECT Public/Granted day:2021-03-18
Information query
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