- Patent Title: I2C bus architecture using shared clock and dedicated data lines
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Application No.: US17307842Application Date: 2021-05-04
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Publication No.: US11520729B2Publication Date: 2022-12-06
- Inventor: Lalan Jee Mishra , Radu Pitigoi-Aron , Sharon Graif , Lior Amarilio , Richard Dominic Wietfeldt
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Qualcomm Incorporated
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F1/08 ; G06F13/20

Abstract:
Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.
Public/Granted literature
- US20220358079A1 I2C BUS ARCHITECTURE USING SHARED CLOCK AND DEDICATED DATA LINES Public/Granted day:2022-11-10
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