A memory device includes a latch circuit suitable for storing an input address as a first latch address in response to a first latch signal, and storing an address, selected between the input address and the first latch address, as a second latch address in response to a second latch signal, a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal corresponding to the determination result, in response to a test mode signal, and a control signal generation circuit suitable for comparing the input address to the first and second latch addresses in response to the detection signal, and selectively enabling the first and second latch signals according to the comparison result.