Invention Grant
- Patent Title: Dynamic logical page sizes for memory devices
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Application No.: US17117907Application Date: 2020-12-10
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Publication No.: US11537527B2Publication Date: 2022-12-27
- Inventor: Sharath Chandra Ambula , David Aaron Palmer , Venkata Kiran Kumar Matturi , Sri Ramya Pinisetty , Sushil Kumar
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G06F12/1009
- IPC: G06F12/1009

Abstract:
Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.
Public/Granted literature
- US20220188244A1 DYNAMIC LOGICAL PAGE SIZES FOR MEMORY DEVICES Public/Granted day:2022-06-16
Information query
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