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    Dynamic logical page sizes for memory devices
    2.
    发明授权
    Dynamic logical page sizes for memory devices 有权

    公开(公告)号：US12130747B2

    公开(公告)日：2024-10-29

    申请号：US18081468

    申请日：2022-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Sharath Chandra Ambula ,  David Aaron Palmer ,  Venkata Kiran Kumar Matturi ,  Sri Ramya Pinisetty ,  Sushil Kumar

    IPC: G06F12/1009

    CPC classification number: G06F12/1009 ,  G06F2212/657

    Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

    DYNAMIC LOGICAL PAGE SIZES FOR MEMORY DEVICES
    4.
    发明申请
    DYNAMIC LOGICAL PAGE SIZES FOR MEMORY DEVICES 有权

    公开(公告)号：US20220188244A1

    公开(公告)日：2022-06-16

    申请号：US17117907

    申请日：2020-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Sharath Chandra Ambula ,  David Aaron Palmer ,  Venkata Kiran Kumar Matturi ,  Sri Ramya Pinisetty ,  Sushil Kumar

    IPC: G06F12/1009

    Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

    Write buffer extensions for storage interface controllers
    6.
    发明授权
    Write buffer extensions for storage interface controllers 有权

    公开(公告)号：US11977768B2

    公开(公告)日：2024-05-07

    申请号：US17807838

    申请日：2022-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Sharath Chandra Ambula ,  Sushil Kumar ,  Venkata Kiran Kumar Matturi

    IPC: G06F3/06 ,  G06F1/3234

    CPC classification number: G06F3/0656 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/0679

    Abstract: Methods, systems, and devices for write buffer extensions for storage interface controllers are described. Apparatuses and methods are presented in which a buffer may be used to temporarily store data from an application if the memory device is in an INACTIVE power mode. This may allow the memory device to remain asleep. The buffer may be positioned on the host device so that the power mode of the memory device may not affect it. That way, data may be stored in the buffer without waking up the memory device. If the memory device is in an ACTIVE power mode, the data that has been temporarily stored in the buffer may be sent to the memory device for storage. During read operations, if the requested data is stored in the buffer, it may be used instead of data in the memory device.

    WRITE BUFFER EXTENSIONS FOR STORAGE INTERFACE CONTROLLERS
    7.
    发明公开
    WRITE BUFFER EXTENSIONS FOR STORAGE INTERFACE CONTROLLERS 审中-公开

    公开(公告)号：US20230147027A1

    公开(公告)日：2023-05-11

    申请号：US17807838

    申请日：2022-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Sharath Chandra Ambula ,  Sushil Kumar ,  Venkata Kiran Kumar Matturi

    IPC: G06F3/06 ,  G06F1/3234

    CPC classification number: G06F3/0656 ,  G06F3/0647 ,  G06F3/0625 ,  G06F1/3275 ,  G06F3/0679

    Abstract: Methods, systems, and devices for write buffer extensions for storage interface controllers are described. Apparatuses and methods are presented in which a buffer may be used to temporarily store data from an application if the memory device is in an INACTIVE power mode. This may allow the memory device to remain asleep. The buffer may be positioned on the host device so that the power mode of the memory device may not affect it. That way, data may be stored in the buffer without waking up the memory device. If the memory device is in an ACTIVE power mode, the data that has been temporarily stored in the buffer may be sent to the memory device for storage. During read operations, if the requested data is stored in the buffer, it may be used instead of data in the memory device.

    RATE ADJUSTMENTS FOR A MEMORY INTERFACE
    8.
    发明申请
    RATE ADJUSTMENTS FOR A MEMORY INTERFACE 有权

    公开(公告)号：US20230074643A1

    公开(公告)日：2023-03-09

    申请号：US17889660

    申请日：2022-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Kondalarao Chunchu ,  Niraimathi N S ,  Sharath Chandra Ambula ,  Shobhit Kumar Bhadani ,  Sushil Kumar ,  Vanaja Ambapuram ,  Venkata Kiran Kumar Matturi

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for rate adjustments for a memory interface are described. A host system may communicate with a memory system via an interface according to multiple data transfer rates. For example, the host system may configure the interface to operate according to a first rate. The host system may switch the interface from the first rate to a second rate in response to one or more commands from the host system satisfying one or more parameters such as a threshold quantity of data associated with a command, a threshold quantity of issued commands associated with at least the threshold quantity of data, a threshold quantity of issued and unexecuted commands, or any combination thereof. Based on the switching, the host system may communicate with the memory system via the interface in accordance with the second rate.

    Read operation using compressed memory
    9.
    发明授权
    Read operation using compressed memory 有权

    公开(公告)号：US11886739B2

    公开(公告)日：2024-01-30

    申请号：US17144573

    申请日：2021-01-08

    Applicant: Micron Technology, Inc.

    Inventor： Venkata Kiran Kumar Matturi ,  Tushar Chhabra ,  Sushil Kumar ,  Sharath Chandra Ambula

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0679

    Abstract: Methods, systems, and devices for a read operation using compressed memory are described. An apparatus may include a host system coupled with a non-volatile memory device and a volatile memory device. The host system may store, in the volatile memory device, a compressed copy of data stored in the non-volatile memory device, for example, based on a score assigned to the data. The host system may identify that the compressed copy of the data is stored in the volatile memory device and may transmit a read command to the volatile memory device that includes a logical address associated with a logical block address of the data stored in the non-volatile memory device. The host system may receive the compressed copy of the data from the volatile memory device in response to the read command and may decompress the data.

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