Invention Grant
- Patent Title: Hybrid nanostructure and fin structure device
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Application No.: US16566037Application Date: 2019-09-10
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Publication No.: US11545573B2Publication Date: 2023-01-03
- Inventor: Ta-Chun Lin , Kuo-Hua Pan , Jhon Jhy Liaw
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/02 ; H01L29/66 ; H01L21/8234 ; H01L21/768
Abstract:
A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.
Public/Granted literature
- US20210074841A1 Hybrid Nanostructure and Fin Structure Device Public/Granted day:2021-03-11
Information query
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