A non-volatile memory control technology. In response to a read command, a non-volatile memory interface controller temporarily stores data read from a non-volatile memory to a system memory and, accordingly, asserts a flag in the system memory. Through a write channel provided by the interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from the system memory. A master computing unit reads the system memory through a read channel provided by the interconnect bus, without being delayed by the status checking of the flag. The host bridge controller executes a data detection command or a preset vendor command to issue a write request for programming data in a virtual address, to trigger a handshake between the host bridge controller and the system memory through the write channel. During the handshake, flag checking is achieved.