-
1.发明授权公开(公告)号：US11314571B2
公开(公告)日：2022-04-26
申请号：US16398280
申请日：2019-04-30
Applicant: Silicon Motion, Inc.
Inventor： An-Pang Li
IPC: G06F7/06 , G06F11/07 , G06F9/32 , G06F13/16 , G06F11/20 , G06F9/48 , G06F9/54 , G06F13/24 , G06F3/06 , G06F11/10
Abstract: A multi-processor system with a distributed mailbox architecture and a communication method thereof are provided. The multi-processor system comprises a plurality of processors, each of the processors is correspondingly configured with an exclusive mailbox and an exclusive channel, and the communication method comprises the following steps. When a first processor of the processors needs to communicate with a second processor, the first processor writes data into the exclusive mailbox of the second processor through a public bus; and when the writing of the data has completed, the exclusive mailbox of the second processor sends an interrupt signal to the second processor, after receiving the interrupt signal, the second processor reads the data in the exclusive mailbox through the corresponding exclusive channel.
-
公开(公告)号：US11550740B2
公开(公告)日：2023-01-10
申请号：US17690555
申请日：2022-03-09
Applicant: Silicon Motion, Inc.
Inventor： An-Pang Li
Abstract: A non-volatile memory control technology. In response to a read command, a non-volatile memory interface controller temporarily stores data read from a non-volatile memory to a system memory and, accordingly, asserts a flag in the system memory. Through a write channel provided by the interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from the system memory. A master computing unit reads the system memory through a read channel provided by the interconnect bus, without being delayed by the status checking of the flag. The host bridge controller executes a data detection command or a preset vendor command to issue a write request for programming data in a virtual address, to trigger a handshake between the host bridge controller and the system memory through the write channel. During the handshake, flag checking is achieved.
-
公开(公告)号：US11372800B2
公开(公告)日：2022-06-28
申请号：US17071996
申请日：2020-10-15
Applicant: Silicon Motion, Inc.
Inventor： An-Pang Li
IPC: G06F15/167 , G06F15/78 , G06F13/38 , G06F13/16 , G06F13/40
Abstract: The present invention provides a SoC including a first CPU, a first tightly-coupled memory, a second CPU and a second tightly-coupled memory is disclosed. The first CPU includes a first core circuit, a first level one memory interface and a first level two memory interface. The first tightly-coupled memory is directly coupled to the first level one memory interface, and the first tightly-coupled memory includes a first mailbox. The second CPU includes a second core circuit, a second level one memory interface and a second level two memory interface. The second tightly-coupled memory is directly coupled to the second level one memory interface, and the second tightly-coupled memory includes a second mailbox. When the first CPU sends a command to the second mailbox within the second tightly-coupled memory, the second core circuit directly reads the command from the second mailbox, without going through the second level two memory interface.
-
公开(公告)号：US11651707B2
公开(公告)日：2023-05-16
申请号：US16704688
申请日：2019-12-05
Applicant: Silicon Motion, Inc.
Inventor： An-Pang Li
CPC classification number: G09C1/00 , G06F12/0246 , G06F21/602 , H03M13/09 , H04L9/0631 , G06F2212/7202
Abstract: The invention introduces an apparatus for encrypting and decrypting user data, including a memory, a bypass-flag writing circuit and a flash interface controller. The bypass-flag writing circuit writes a bypass flag in a remaining bit of space of the memory that is originally allocated for storing an End-to-End Data Path Protection (E2E DPP), where the bypass flag indicates whether user data has been encrypted. The flash interface controller reads the user data, the E2E DPP and the bypass flag from the memory and programs the user data, the E2E DPP and the bypass flag into the flash device.
-
公开(公告)号：US11366775B2
公开(公告)日：2022-06-21
申请号：US17152138
申请日：2021-01-19
Applicant: Silicon Motion, Inc.
Inventor： An-Pang Li
Abstract: An efficient control technology for non-volatile memory. In a controller, a host bridge controller and a master computing unit are coupled to a system memory via an interconnect bus, and then coupled to a non-volatile memory interface controller. In response to a read command issued by a host, the non-volatile memory interface controller temporarily stores data read from a non-volatile memory to the system memory and, accordingly, asserts a flag in the system memory. Through a first channel provided by the interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from system memory and returns the data to the host. The master computing unit reads the system memory through a second channel provided by the interconnect bus, without being delayed by the status checking of the flag.
-
Patent Agency Ranking
公开(公告)号：US11526454B2
公开(公告)日：2022-12-13
申请号：US17690535
申请日：2022-03-09
Applicant: Silicon Motion, Inc.
Inventor： An-Pang Li
Abstract: A non-volatile memory control technology. In response to a read command, a non-volatile memory interface controller temporarily stores data read from a non-volatile memory to the system memory and, accordingly, asserts a flag in the system memory. Through a flag reading channel provided by a interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from the system memory. A master computing unit reads the system memory through a data reading channel provided by the interconnect bus, without being delayed by the status checking of the flag. The interconnect bus further provides a flag writing channel and a data writing channel.
-
公开(公告)号：US11334415B2
公开(公告)日：2022-05-17
申请号：US16503504
申请日：2019-07-04
Applicant: Silicon Motion, Inc.
Inventor： An-Pang Li
IPC: G06F11/07 , G06F9/32 , G06F13/16 , G06F11/20 , G06F9/48 , G06F9/54 , G06F13/24 , G06F3/06 , G06F11/10 , G06F11/22
Abstract: A data storage device and a method for sharing memory of controller thereof are provided. The data storage device comprises a non-volatile memory and a controller, which is electrically coupled to the non-volatile memory and comprises an access interface, a redundant array of independent disks (RAID) error correcting code (ECC) engine and a central processing unit (CPU). The CPU has a first memory for storing temporary data, the RAID ECC engine has a second memory, and the controller maps the unused memory space of the second memory to the first memory to be virtualized as part of the first memory when the second memory is not fully used so that the CPU can also use the unused memory space of the second memory to store the temporary data.
-
公开(公告)号：US11216207B2
公开(公告)日：2022-01-04
申请号：US17010420
申请日：2020-09-02
Applicant: Silicon Motion, Inc.
Inventor： An-Pang Li
Abstract: The invention introduces a method for programming data of page groups into flash units to include steps for: obtaining, by a host interface (I/F) controller, user data of a page group from a host side, wherein the page group comprises multiple pages; storing, by the host I/F controller, the user data on the pages in a random access memory (RAM) through a bus architecture, outputting the user data on the pages to an engine via an I/F, and enabling the engine to calculate a parity of the page group according to the user data on the pages; obtaining, by a direct memory access (DMA) controller, the parity of the page group from the engine and storing the parity of the page group in the RAM through the bus architecture; and obtaining, by a flash I/F controller, the user data on the pages and the parity of the page group from the RAM through the bus architecture, and programming the user data on the pages and the parity of the page group into a flash module.
-
公开(公告)号：US11704054B1
公开(公告)日：2023-07-18
申请号：US17569451
申请日：2022-01-05
Applicant: Silicon Motion, Inc.
Inventor： An-Pang Li
CPC classification number: G06F3/0656 , G06F3/0604 , G06F3/0622 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2212/72
Abstract: A method for performing access management of a memory device with aid of buffer usage reduction control and associated apparatus are provided. The method includes: determining whether any host command among a plurality of host commands from a host device is a trim-related read command, wherein the trim-related read command represents a read command indicating that reading from at least one trimmed location is required; in response to the any host command being the trim-related read command, determining an estimated trim-related read operation count regarding a data buffer according to a trimmed range of the at least one trimmed location and a predetermined unit size of accessing the data buffer; writing predetermined trimmed data having the predetermined unit size into the data buffer; and controlling a transmission interface circuit to read the predetermined trimmed data from the data buffer multiple times, for being returned to the host device.
-
10.发明公开公开(公告)号：US20230214154A1
公开(公告)日：2023-07-06
申请号：US17569451
申请日：2022-01-05
Applicant: Silicon Motion, Inc.
Inventor： An-Pang Li
CPC classification number: G06F3/0656 , G06F3/0659 , G06F3/0604 , G06F3/0622 , G06F3/0679 , G06F12/0246 , G06F2212/72
Abstract: A method for performing access management of a memory device with aid of buffer usage reduction control and associated apparatus are provided. The method includes: determining whether any host command among a plurality of host commands from a host device is a trim-related read command, wherein the trim-related read command represents a read command indicating that reading from at least one trimmed location is required; in response to the any host command being the trim-related read command, determining an estimated trim-related read operation count regarding a data buffer according to a trimmed range of the at least one trimmed location and a predetermined unit size of accessing the data buffer; writing predetermined trimmed data having the predetermined unit size into the data buffer; and controlling a transmission interface circuit to read the predetermined trimmed data from the data buffer multiple times, for being returned to the host device.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.012 seconds)
