Systems and methods are disclosed for checker cores for fault tolerant processing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions of an instruction set; an outer memory system configured to store instructions and data; and a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core. For example, data flow from the processor core to the checker core may be limited to committed instruction packets received via dedicated a wire bundle.