公开(公告)号：US20240303205A1

公开(公告)日：2024-09-12

申请号：US18579134

申请日：2022-06-06

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Yann Loisel ,  John Ingalls ,  Shubhendu Sekhar Mukherjee

IPC: G06F11/07

CPC classification number: G06F11/0787

Abstract: Systems and methods are disclosed for error management in a system on a chip with a securely partitioned memory space. For example, an integrated circuit (e.g., a processor) for executing instructions includes a world identifier checker circuitry configured to check memory requests for one or more memory mapped resources that are received via the bus that have been tagged with a world identifier to determine whether to allow or reject access based on the tagged world identifier; a world identifier checker circuitry configured to compare the tagged world identifier to a world list for a resource that specifies which world identifiers supported by the integrated circuit are authorized for access to the resource; and a data store configured to store world error data, including the tagged world identifier of a memory request that has been rejected by the world identifier checker circuitry.

公开(公告)号：US20230315649A1

公开(公告)日：2023-10-05

申请号：US18024262

申请日：2021-09-01

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F12/14 ,  G06F21/62 ,  G06F9/30

CPC classification number: G06F12/1458 ,  G06F21/6218 ,  G06F9/30036 ,  G06F2212/1052

Abstract: Systems and methods are disclosed for memory protection for vector operations. For example, a method includes fetching a vector memory instruction using a processor core including a pipeline configured to execute instructions, including constant-stride vector memory instructions; partitioning a vector that is identified by the vector memory instruction into a subvector of a maximum length, greater than one, and one or more additional subvectors with lengths less than or equal to the maximum length; checking, using a memory protection circuit, whether accessing elements of the subvector will cause a memory protection violation; and accessing the elements of the subvector before checking, using the memory protection circuit, whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation.

公开(公告)号：US11347507B2

公开(公告)日：2022-05-31

申请号：US16241455

申请日：2019-01-07

Applicant: SiFive, Inc.

Inventor： Alex Solomatnikov ,  Krste Asanovic

IPC: G06F9/30 ,  G06F12/0815 ,  G06F12/1027 ,  G06F12/02 ,  G06F9/50 ,  G06F9/355

Abstract: Systems and methods are disclosed for secure control flow prediction. Some implementations may be used to eliminate or mitigate the Spectre-class of attacks in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions includes a control flow predictor with entries that include respective indications of whether the entry has been activated for use in a current process, wherein the integrated circuit is configured to access the indication in one of the entries that is associated with a control flow instruction that is scheduled for execution; determine, based on the indication, whether the entry of the control flow predictor associated with the control flow instruction is activated for use in a current process; and responsive to a determination that the entry is not activated for use in the current process, apply a constraint on speculative execution based on control flow prediction for the control flow instruction.

公开(公告)号：US20240160449A1

公开(公告)日：2024-05-16

申请号：US18282728

申请日：2022-03-28

Applicant: SiFive, Inc.

Inventor： David Parry ,  Drew Barbier ,  Josh Smith ,  Alexandre Solomatnikov ,  Krste Asanovic

IPC: G06F9/32 ,  G06F9/30

CPC classification number: G06F9/327 ,  G06F9/30123

Abstract: Systems and methods are disclosed for a configurable interconnect address remapper with event detection. For example, an integrated circuit can include a processor core configured to execute instructions. The processor core includes region registers defined by a From Address range and a To Address, a register storing a number of regions defined in the integrated circuit, interrupt enable registers associated with each pair of region registers, and event flags associated with each pair of region registers; an interconnection system handling transactions from the processor core; an interconnect address remapper translating an address associated with a transaction using the one or more pair of region registers; and an interrupt controller receiving an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one raised event flags when at least one of the one or more pair of region registers matches the transaction address.

公开(公告)号：US20240020124A1

公开(公告)日：2024-01-18

申请号：US18345007

申请日：2023-06-30

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic

IPC: G06F9/30

CPC classification number: G06F9/30101 ,  G06F9/3012

Abstract: Systems and methods are disclosed for supporting multiple vector lengths with a configurable vector register file. For example, an integrated circuit (e.g., a processor) includes a data store configured to store a vector length parameter; a processor core including a vector register, wherein the processor core is configured to: while a first value of the vector length parameter is stored in the data store, store a single architectural register of an instruction set architecture in the vector register; and, while a second value of the vector length parameter is stored in the data store, store multiple architectural registers of the instruction set architecture in respective disjoint portions of the vector register. For example, the integrated circuit may be used to emulate a processor with smaller vector registers for the purpose of migrating a thread to a processor core of the integrated circuit for continued execution.

公开(公告)号：US20230305852A1

公开(公告)日：2023-09-28

申请号：US18017792

申请日：2021-07-23

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/3013

Abstract: Systems and methods are disclosed for register renaming. For example, an integrated circuit is described that includes a first cluster including a first set of physical registers and a first execution resource circuit, wherein the inputs for operations of the first execution resource circuit are of a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the inputs for operations of the second execution resource circuit are of a second data type that is different than the first data type; and a register renaming circuit configured to: determine a data type prediction for a result of a first instruction that will be stored in a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be stored in a physical register of the first set of physical registers.

公开(公告)号：US11687342B2

公开(公告)日：2023-06-27

申请号：US17418933

申请日：2019-12-12

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F12/0875 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/3802 ,  G06F9/30047 ,  G06F9/321 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3816 ,  G06F9/3861 ,  G06F12/0875 ,  G06F2212/452

Abstract: Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.

公开(公告)号：US20210303300A1

公开(公告)日：2021-09-30

申请号：US16856462

申请日：2020-04-23

Applicant: SiFive, Inc.

Inventor： Joshua Smith ,  Krste Asanovic ,  Andrew Waterman

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.

公开(公告)号：US11048515B2

公开(公告)日：2021-06-29

申请号：US16553839

申请日：2019-08-28

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F12/0875

Abstract: Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.

公开(公告)号：US20240338320A1

公开(公告)日：2024-10-10

申请号：US18747399

申请日：2024-06-18

Applicant: SiFive, Inc.

Inventor： Perrine Peresse ,  Shubhendu Sekhar Mukherjee ,  Krste Asanovic

IPC: G06F12/1009 ,  G06F12/0882 ,  G06F12/1045

CPC classification number: G06F12/1009 ,  G06F12/0882 ,  G06F12/1063

Abstract: Systems and methods are disclosed for page table entry caches with multiple tag lengths. For example, an integrated circuit (e.g., a processor) includes a page table walk circuitry including a page table entry cache, in which the page table walk circuitry is configured to access a multi-level page table, and in which a first entry of the page table entry cache combines a first number of multiple levels and a second entry of the page table entry cache combines a second number of multiple levels that is different from the first number of multiple levels.