Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
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Application No.: US17026562Application Date: 2020-09-21
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Publication No.: US11563102B2Publication Date: 2023-01-24
- Inventor: Chun-Chieh Lu , Carlos H. Diaz , Chih-Sheng Chang , Cheng-Yi Peng , Ling-Yen Yeh
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L29/51 ; H01L29/78 ; H01L21/324 ; H01L21/02 ; H01L49/02 ; H01L29/66 ; H01L21/28

Abstract:
In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
Public/Granted literature
- US20210005734A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-01-07
Information query
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