Invention Grant
- Patent Title: Integrated power delivery board for delivering power to an ASIC with bypass of signal vias in a printed circuit board
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Application No.: US17220033Application Date: 2021-04-01
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Publication No.: US11564317B2Publication Date: 2023-01-24
- Inventor: Shobhana Punjabi , Kan Seto , Straty Argyrakis , Joel Richard Goergen , Paul Lachlan Mantiply , Richard Anthony O'Brien
- Applicant: CISCO TECHNOLOGY, INC.
- Applicant Address: US CA San Jose
- Assignee: CISCO TECHNOLOGY, INC.
- Current Assignee: CISCO TECHNOLOGY, INC.
- Current Assignee Address: US CA San Jose
- Main IPC: H05K1/14
- IPC: H05K1/14 ; H05K1/18 ; H05K1/02 ; H05K1/11

Abstract:
In one embodiment, an apparatus generally comprises a printed circuit board comprising a first side, a second side, and a plurality of power vias extending from the first side to the second side, the first side configured for receiving an application specific integrated circuit (ASIC), and a power delivery board mounted on the second side of the printed circuit board and comprising a power plane interconnected with power vias in the power delivery board to electrically couple voltage regulator modules and the ASIC. The voltage regulator modules are mounted on the second side of the printed circuit board.
Public/Granted literature
Information query