公开(公告)号：US20210219426A1

公开(公告)日：2021-07-15

申请号：US17220033

申请日：2021-04-01

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Shobhana Punjabi ,  Kan Seto ,  Straty Argyrakis ,  Joel Richard Goergen ,  Paul Lachlan Mantiply ,  Richard Anthony O'Brien

IPC: H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11

Abstract: In one embodiment, an apparatus generally comprises a printed circuit board comprising a first side, a second side, and a plurality of power vias extending from the first side to the second side, the first side configured for receiving an application specific integrated circuit (ASIC), and a power delivery board mounted on the second side of the printed circuit board and comprising a power plane interconnected with power vias in the power delivery board to electrically couple voltage regulator modules and the ASIC. The voltage regulator modules are mounted on the second side of the printed circuit board.

公开(公告)号：US10469200B2

公开(公告)日：2019-11-05

申请号：US15888905

申请日：2018-02-05

Applicant: Cisco Technology, Inc.

Inventor： Paul Lachlan Mantiply ,  Peter Malcolm Barnes ,  Oded Trainin ,  John Joseph Williams, Jr.

IPC: H04L1/00 ,  H04L1/08

Abstract: Techniques for reducing latency associated with metaframe error correction. Embodiments receive, via a first port of a plurality of ports, a stream of bits within a metaframe. Upon evaluating a first cyclic redundancy check (CRC) for a first portion of the stream of bits and determining that the first CRC is valid, a measure of latency incurred in transmitting the first portion is reduced, relative to first performing forward error correction (FEC) decoding for the first portion prior to transmission, by transmitting the first portion of the stream of bits without performing FEC decoding for the first portion of the stream of bits. Upon evaluating a second CRC for a second portion of the stream of bits and determining that the second CRC is invalid, FEC decoding is performed for the second portion of the stream of bits before forwarding the second portion of the stream of bits.

公开(公告)号：US11564317B2

公开(公告)日：2023-01-24

申请号：US17220033

申请日：2021-04-01

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Shobhana Punjabi ,  Kan Seto ,  Straty Argyrakis ,  Joel Richard Goergen ,  Paul Lachlan Mantiply ,  Richard Anthony O'Brien

IPC: H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11

Abstract: In one embodiment, an apparatus generally comprises a printed circuit board comprising a first side, a second side, and a plurality of power vias extending from the first side to the second side, the first side configured for receiving an application specific integrated circuit (ASIC), and a power delivery board mounted on the second side of the printed circuit board and comprising a power plane interconnected with power vias in the power delivery board to electrically couple voltage regulator modules and the ASIC. The voltage regulator modules are mounted on the second side of the printed circuit board.

公开(公告)号：US10999930B2

公开(公告)日：2021-05-04

申请号：US16222913

申请日：2018-12-17

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Shobhana Punjabi ,  Kan Seto ,  Straty Argyrakis ,  Joel Richard Goergen ,  Paul Lachlan Mantiply ,  Richard Anthony O'Brien

IPC: H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11

Abstract: In one embodiment, an apparatus generally comprises a power delivery board for integration with a printed circuit board, the power delivery board comprising a power plane for delivering power from a voltage regulator module to an application specific integrated circuit (ASIC) mounted on a first side of the printed circuit board. The power plane in the power delivery board interconnects with power vias in the power delivery board for vertical alignment with the ASIC through power vias in the printed circuit board to electrically couple the voltage regulator module and the ASIC when the power delivery board is mounted on a second side of the printed circuit board.

公开(公告)号：US09887806B2

公开(公告)日：2018-02-06

申请号：US14796792

申请日：2015-07-10

Applicant: Cisco Technology, Inc.

Inventor： Paul Lachlan Mantiply ,  Peter Malcolm Barnes ,  Oded Trainin ,  John Joseph Williams, Jr.

IPC: H04L1/00 ,  H04L1/08

CPC classification number: H04L1/0057 ,  H04L1/0007 ,  H04L1/0009 ,  H04L1/0053 ,  H04L1/0061 ,  H04L1/08

Abstract: Embodiments generally provide techniques for data framing and error correction for communications on a link. Embodiments include receiving a stream of bits within a metaframe. Upon determining that a cyclic redundancy check (CRC) for a portion of the stream of bits is valid, the portion of the stream of bits is forwarded without performing forward error correction (FEC) decoding for the first portion. Upon determining that a CRC for the portion of the stream of bits is invalid, FEC decoding is performed for the portion before forwarding the portion of the stream of bits. Embodiments also include generating a metaframe for transmission over a link, and upon determining that a current measure of network throughput is less than a predefined threshold amount of network throughput, inserting one or more checkpoints into the metaframe to create different segments of the metaframe. The metaframe is then transmitted over the link.