- Patent Title: Temperature management for a memory device using memory trim sets
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Application No.: US16685300Application Date: 2019-11-15
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Publication No.: US11567682B2Publication Date: 2023-01-31
- Inventor: Ting Luo , Ankit Vinod Vashi , Xiangang Luo , Jianmin Huang
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
Techniques disclosed herein can be used to improve cross-temperature coverage of memory devices and improve memory device reliability in cross-temperature conditions. More specifically, a memory trim set can be selected from multiple candidate memory trim sets when performing a memory operation (such as a memory write operation), based on a temperature metric and a P/E cycle metric for the memory device. The candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation. The temperature metric can be indicative of a temperature of at least a region of the memory device (e.g., the entire device, a memory plane, a memory block, etc.), and the P/E cycle metric can be indicative of a number of P/E cycles performed by the memory device within a selected time interval.
Public/Granted literature
- US20210149564A1 TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE Public/Granted day:2021-05-20
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