Apparatus might include a controller configured to cause the apparatus to program a plurality of memory cells from a first data state to a second data state higher than the first data state, determine a respective first voltage level of a control gate voltage deemed to cause each memory cell of a first and second subset of memory cells of the plurality of memory cells to reach the second data state, determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the first subset of memory cells to reach a third data state higher than the second data state, and determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the second subset of memory cells to reach a fourth data state higher than the third data state.