- Patent Title: Semiconductor devices including a lower semiconductor package, an upper semiconductor package on the lower semiconductor package, and a connection pattern between the lower semiconductor package and the upper semiconductor package
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Application No.: US17376570Application Date: 2021-07-15
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Publication No.: US11600545B2Publication Date: 2023-03-07
- Inventor: Ji Hwang Kim , Jong Bo Shim , Jang Woo Lee , Yung Cheol Kong , Young Hoon Hyun
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2018-0161564 20181214
- Main IPC: H01L23/367
- IPC: H01L23/367 ; H01L23/31 ; H01L23/00

Abstract:
A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.
Public/Granted literature
- US20210343617A1 SEMICONDUCTOR PACKAGES Public/Granted day:2021-11-04
Information query
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