公开(公告)号：US10680025B2

公开(公告)日：2020-06-09

申请号：US15952449

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Bo Shim ,  Cha Jea Jo ,  Sang Uk Han

IPC: H01L27/146 ,  H01L23/00 ,  H01L27/30

Abstract: A semiconductor package includes a package substrate, an image sensor disposed on the package substrate, and a bonding layer disposed between the package substrate and the image sensor, and including a first region and a second region, the second region has a modulus of elasticity lower than that of the first region and is disposed on a periphery of the first region.

公开(公告)号：US12283578B2

公开(公告)日：2025-04-22

申请号：US17710830

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong Hyun Lee ,  Hwan Pil Park ,  Jong Bo Shim

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor package includes; a substrate including a first insulating layer and a first conductive pattern in the first insulating layer, a first semiconductor chip on the substrate, an interposer spaced apart from the first semiconductor chip in a direction perpendicular to an upper surface of the substrate and including a second insulating layer and a second conductive pattern in the second insulating layer, a first element between the first semiconductor chip and the interposer, a connection member between the substrate and the interposer, and a mold layer covering side surfaces of the first semiconductor chip and side surfaces of the first element.

公开(公告)号：US09966364B2

公开(公告)日：2018-05-08

申请号：US15435285

申请日：2017-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gun Ho Chang ,  Jong Bo Shim ,  Cha Je Jo

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0912 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: A semiconductor package comprising: a substrate including an external connection terminal and a cavity; a first semiconductor chip disposed in the cavity, the first semiconductor chip including a first pad and a second pad different from the first pad, the first pad and the second pad being disposed on a first surface of the first semiconductor chip; a metal line disposed on the substrate and the first semiconductor chip and electrically connecting the first pad of the first semiconductor chip with the external connection terminal of the substrate; a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip including a third pad disposed on a second surface of the second semiconductor chip facing the first semiconductor chip; and a connection terminal electrically connecting the second pad of the first semiconductor chip with the third pad of the second semiconductor chip, the connection terminal being not electrically connected to the metal line.

公开(公告)号：US20240128173A1

公开(公告)日：2024-04-18

申请号：US18320456

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Yong Park ,  Jong Bo Shim ,  Dae Hun Lee ,  Choong Bin Yim

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L21/563 ,  H01L21/565 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L24/13 ,  H01L24/14 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14131

Abstract: A semiconductor package includes a first package substrate having a first region and a second region, which do not overlap each other, a first connection element having a first height on the first region, a first semiconductor chip having a second height connected to the first connection element, a second connection element having a third height on the second region, a third connection element having a fourth height on the second connection element and electrically connected to the second connection element, a second package on the third connection element, the second package including a second package substrate and a second semiconductor chip, and a first mold layer covering at least a portion of the first semiconductor chip, covering at least a portion of the second connection element, covering the first package substrate, exposing upper surfaces of the first semiconductor chip and the second connection element, and having a fifth height.

公开(公告)号：US20190103432A1

公开(公告)日：2019-04-04

申请号：US15952449

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Bo Shim ,  Cha Jea Jo ,  Sang Uk Han

IPC: H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate, an image sensor disposed on the package substrate, and a bonding layer disposed between the package substrate and the image sensor, and including a first region and a second region, the second region has a modulus of elasticity lower than that of the first region and is disposed on a periphery of the first region.

公开(公告)号：US20230207416A1

公开(公告)日：2023-06-29

申请号：US18178170

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Jong Bo Shim ,  Jang Woo Lee ,  Yung Cheol Kong ,  Young Hoon Hyun

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/02371

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

公开(公告)号：US11600545B2

公开(公告)日：2023-03-07

申请号：US17376570

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang Kim ,  Jong Bo Shim ,  Jang Woo Lee ,  Yung Cheol Kong ,  Young Hoon Hyun

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

公开(公告)号：US11069592B2

公开(公告)日：2021-07-20

申请号：US16582418

申请日：2019-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang Kim ,  Jong Bo Shim ,  Jang Woo Lee ,  Yung Cheol Kong ,  Young Hoon Hyun

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

公开(公告)号：US12057366B2

公开(公告)日：2024-08-06

申请号：US18178170

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang Kim ,  Jong Bo Shim ,  Jang Woo Lee ,  Yung Cheol Kong ,  Young Hoon Hyun

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L23/3157 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/02371

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

公开(公告)号：US11908806B2

公开(公告)日：2024-02-20

申请号：US17501008

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Ho Kim ,  Ji Hwang Kim ,  Hwan Pil Park ,  Jong Bo Shim

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/56 ,  H01L23/42 ,  H01L21/48

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838

Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.