- Patent Title: Well pick-up region design for improving memory macro performance
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Application No.: US16657421Application Date: 2019-10-18
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Publication No.: US11600623B2Publication Date: 2023-03-07
- Inventor: Chih-Chuan Yang , Chang-Ta Yang , Ping-Wei Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/11
- IPC: H01L27/11 ; G11C11/412 ; G06F30/30

Abstract:
Well pick-up regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region; a first well pick-up (WPU) region; a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type; and a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type, wherein the first well has a first portion in the circuit region and a second portion in the first WPU region, and the second portion of the first well has a width larger than the first portion of the first well along a second direction perpendicular to the first direction.
Public/Granted literature
- US20200168616A1 Well Pick-Up Region Design for Improving Memory Macro Performance Public/Granted day:2020-05-28
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