公开(公告)号：US11948829B2

公开(公告)日：2024-04-02

申请号：US17682425

申请日：2022-02-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chang-Ta Yang

IPC分类号： H01L21/762 ,  H01L21/3065 ,  H10B10/00

CPC分类号： H01L21/76224 ,  H01L21/3065 ,  H01L21/76232 ,  H10B10/12

摘要： A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.

公开(公告)号：US11264268B2

公开(公告)日：2022-03-01

申请号：US16450278

申请日：2019-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chang-Ta Yang

IPC分类号： H01L21/762 ,  H01L21/3065 ,  H01L27/11

摘要： A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.

公开(公告)号：US20210313463A1

公开(公告)日：2021-10-07

申请号：US17352587

申请日：2021-06-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/762

摘要： A semiconductor device comprises a memory macro including a well pick-up (WPU) area oriented lengthwise along a first direction, and memory bit areas adjacent to the WPU area. In the WPU area, the memory macro includes n-type and p-type wells arranged alternately along the first direction with well boundaries between adjacent wells; gate structures over the wells and oriented lengthwise along the first direction; a first dielectric layer disposed at each of the well boundaries; first contact features disposed over one of the p-type wells; and second contact features disposed over one of the n-type wells. From a top view, the first dielectric layer extends along a second direction perpendicular to the first direction and separates all the gate structures in the first WPU area, the first contact features are disposed between the gate structures, and the second contact features are disposed between the gate structures.

公开(公告)号：US11910585B2

公开(公告)日：2024-02-20

申请号：US17873626

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC分类号： H10B10/00 ,  G06F30/30 ,  G11C11/412

CPC分类号： H10B10/00 ,  G06F30/30 ,  G11C11/412

摘要： Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.

公开(公告)号：US11728432B2

公开(公告)日：2023-08-15

申请号：US17352587

申请日：2021-06-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/762

CPC分类号： H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76224

摘要： A semiconductor device comprises a memory macro including a well pick-up (WPU) area oriented lengthwise along a first direction, and memory bit areas adjacent to the WPU area. In the WPU area, the memory macro includes n-type and p-type wells arranged alternately along the first direction with well boundaries between adjacent wells; gate structures over the wells and oriented lengthwise along the first direction; a first dielectric layer disposed at each of the well boundaries; first contact features disposed over one of the p-type wells; and second contact features disposed over one of the n-type wells. From a top view, the first dielectric layer extends along a second direction perpendicular to the first direction and separates all the gate structures in the first WPU area, the first contact features are disposed between the gate structures, and the second contact features are disposed between the gate structures.

公开(公告)号：US10083970B2

公开(公告)日：2018-09-25

申请号：US15446260

申请日：2017-03-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chia-Hao Pao ,  Chang-Ta Yang ,  Feng-Ming Chang ,  Ping-Wei Wang

IPC分类号： H01L27/11 ,  H01L23/52 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  G11C11/41 ,  G11C5/06 ,  G11C11/419 ,  H01L23/528 ,  G11C11/412

CPC分类号： H01L27/1104 ,  G11C5/06 ,  G11C5/063 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/419 ,  H01L23/528 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7827

摘要： An SRAM includes an SRAM array including a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.

公开(公告)号：US20180138185A1

公开(公告)日：2018-05-17

申请号：US15354052

申请日：2016-11-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jordan Hsu ,  Yu-Kuan Lin ,  Shau-Wei Lu ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Hung Lo

IPC分类号： H01L27/11 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/1104 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/1052 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66803

摘要： A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate. The second transistor is disposed on the substrate. A gate of the first transistor and a gate of the second transistor are integrally formed, and the first transistor and the second transistor have different threshold voltages.

公开(公告)号：US11856745B2

公开(公告)日：2023-12-26

申请号：US17860977

申请日：2022-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC分类号： H10B10/00 ,  G11C11/412 ,  H01L29/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/768

CPC分类号： H10B10/12 ,  G11C11/412 ,  H01L21/76895 ,  H01L23/5226 ,  H01L27/0207 ,  H01L29/66477 ,  H10B10/18

摘要： An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

公开(公告)号：US11043595B2

公开(公告)日：2021-06-22

申请号：US16441217

申请日：2019-06-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/762

摘要： A semiconductor device includes a memory macro having first and second well pick-up (WPU) areas along first and second edges of the memory macro, respectively, and memory bit areas between the first and the second WPU areas. The first and second WPU areas are oriented lengthwise generally along a first direction. In each of the first and second WPU areas, the memory macro includes n-type wells and p-type wells arranged alternately along the first direction with a well boundary between each of the n-type wells and the adjacent p-type well. The memory macro further includes active regions; an isolation structure; gate structures, and a first dielectric layer that is disposed at each of the well boundaries. From a top view, the first dielectric layer extends generally along a second direction perpendicular to the first direction and through all the gate structures in the first and the second WPU areas.

公开(公告)号：US20200168616A1

公开(公告)日：2020-05-28

申请号：US16657421

申请日：2019-10-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC分类号： H01L27/11 ,  G06F17/50 ,  G11C11/412

摘要： Well pick-up regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region; a first well pick-up (WPU) region; a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type; and a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type, wherein the first well has a first portion in the circuit region and a second portion in the first WPU region, and the second portion of the first well has a width larger than the first portion of the first well along a second direction perpendicular to the first direction.