Invention Grant
- Patent Title: Ingaas epi structure and wet etch process for enabling III-v GAA in art trench
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Application No.: US15529481Application Date: 2014-12-24
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Publication No.: US11631737B2Publication Date: 2023-04-18
- Inventor: Sanaz K. Gardner , Willy Rachmady , Matthew V. Metz , Gilbert Dewey , Jack T. Kavalieros , Chandra S. Mohapatra , Anand S. Murthy , Nadia M. Rahhal-Orabi , Nancy M. Zelick , Tahir Ghani
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2014/072396 WO 20141224
- International Announcement: WO2016/105426 WO 20160630
- Main IPC: H01L29/205
- IPC: H01L29/205 ; H01L29/06 ; H01L29/66 ; H01L29/78 ; H01L21/762 ; H01L29/267 ; H01L29/423 ; H01L29/786 ; H01L29/10 ; H01L29/04

Abstract:
Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.
Public/Granted literature
- US20170263706A1 INGAAS EPI STRUCTURE AND WET ETCH PROCESS FOR ENABLING III-V GAA IN ART TRENCH Public/Granted day:2017-09-14
Information query
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