Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
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Application No.: US17179954Application Date: 2021-02-19
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Publication No.: US11631755B2Publication Date: 2023-04-18
- Inventor: Chun-Chieh Lu , Cheng-Yi Peng , Chien-Hsing Lee , Ling-Yen Yeh , Chih-Sheng Chang , Carlos H. Diaz
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/28 ; H01L29/94 ; H01L29/51 ; H01L29/78

Abstract:
In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
Public/Granted literature
- US20210175342A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-06-10
Information query
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