- 专利标题: Method of forming a semiconductor structure having a gate structure electrically connected to a word line
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申请号: US17659493申请日: 2022-04-18
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公开(公告)号: US11641734B2公开(公告)日: 2023-05-02
- 发明人: Szu-Yao Chang
- 申请人: NANYA TECHNOLOGY CORPORATION
- 申请人地址: TW New Taipei
- 专利权人: NANYA TECHNOLOGY CORPORATION
- 当前专利权人: NANYA TECHNOLOGY CORPORATION
- 当前专利权人地址: TW New Taipei
- 代理机构: CKC & Partners Co., LLC
- 主分类号: G11C8/14
- IPC分类号: G11C8/14 ; G11C11/402 ; H01L49/02
摘要:
A method of forming a semiconductor structure includes forming a capacitor on a substrate. A recess is formed in the capacitor. A drain region is formed in the recess. A word line is formed on the drain region. A gate structure is formed on the drain region, and the gate structure is electrically connected to the word line. A first bit line is formed on the gate structure, such that the first bit line servers as a source region.
公开/授权文献
- US20220238530A1 METHOD OF FORMING SEMICONDUCTOR STRUCTURE 公开/授权日:2022-07-28