Invention Grant
- Patent Title: Neural network classifier using array of three-gate non-volatile memory cells
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Application No.: US17471099Application Date: 2021-09-09
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Publication No.: US11646075B2Publication Date: 2023-05-09
- Inventor: Hieu Van Tran , Steven Lemke , Vipin Tiwari , Nhan Do , Mark Reiten
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- The original application number of the division: US16382045 2019.04.11
- Main IPC: G11C11/54
- IPC: G11C11/54 ; H01L29/423 ; G11C16/04 ; G11C16/10 ; G11C16/14 ; H01L29/788 ; G06N3/045

Abstract:
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.
Public/Granted literature
- US20210407588A1 NEURAL NETWORK CLASSIFIER USING ARRAY OF THREE-GATE NON-VOLATILE MEMORY CELLS Public/Granted day:2021-12-30
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